Algorithmic chip-design loops

A loop that takes a parameterised generator and a search space and runs each candidate through lint, bit- and cycle-exact RTL simulation, a gate-netlist simulation check and Yosys synthesis, caching by design hash and logging every evaluation as JSON. On chip-accel’s MAC engine (40 designs) all candidates pass; synthesis and the gate-level check take 99% of the 424 s of wall time and RTL simulation under 1%. The Pareto front matches chip-accel’s. A follow-up reuses one Yosys run for the gate check and the score: identical metrics on all 40 designs and 50% less wall time (561 s to 280 s, single timing runs). Stylised: one design family, generic-gate counts, simulation-based (not formal) equivalence, no place and route.

The grid orders from eda-gridorder are replayed on the MAC and FIR design families of eda-surrogate (36 designs each, Yosys cell count against analytic cycles; nothing new synthesised). Lexicographic is not reliably bad but arbitrary: worst on MAC (90% of the front’s hypervolume after 25 evaluations against 3–4 for the others), best on FIR (4 against 5–9), because it wins exactly when the front sits at the first corner of the leading axis. Farthest-point beat random from about 6 evaluations on every table and found FIR’s full front in 16 evaluations against 28 for random; Halton was mixed. The harness gains an order option on its grid proposer. Stylised: two small families, two objectives, deterministic orders are single draws.

The lexicographic grid that the harness ships is replayed against Halton, farthest-point and Latin orders and random shuffles on the 80-design table from eda-proposers (stdlib only, nothing new simulated). Lexicographic scores worse than all 300 random orders up to 30 evaluations and needs 75 evaluations for the whole front; a Halton order reaches 90% of the front's hypervolume in 7 evaluations against a median 17 for random, while random-start farthest-point and Latin orders gain only +0.010 to +0.042 over random from 8 to 20 evaluations and nothing by 40. Stylised: one small table, and the deterministic orders are single draws with no interval.

Random search, a grid, simulated annealing, a genetic algorithm, NSGA-II and a TPE-style Bayesian method are compared at equal evaluation budgets on an 80-design space (MAC lanes × bit width × ABC script) of a toy quantised-MLP accelerator, using Pareto hypervolume over 100 seeds. TPE reaches 0.917 of the true-front hypervolume at 16 evaluations against 0.891 for random, and 0.980 against 0.943 at 30; annealing trails random throughout. Stylised: the space is tiny (random search at 40 evaluations already scores 0.965), hyperparameters are untuned, objectives are generic-gate counts, and nothing is said about real chips.

A three-rung ladder over 40 logged MAC-engine designs: a free analytic model (cells ≈ lanes×bits²), cycle-accurate simulation, and Yosys synthesis. The analytic rung ranks the cells×cycles objective with Spearman 0.74 against synthesis (0.95 for cells alone) and finds 2 of the 5 best designs. Successive halving that screens on the cheap rungs reaches the optimum with certainty at 20 s of tool time, against 0.10 for random search at the same budget and 205 s for synthesising everything. Stylised: one toy design family with its optimum at a corner, no place-and-route rung, and the search is a replay over the committed log.

A surrogate for Yosys generic-gate cell counts, trained on 24 word-level features (multiplier, adder, mux and register sizes read after proc; opt, about 30× cheaper than synthesis) over 133 designs in four generator families I wrote: MAC engines, FIR filters, ALUs and sorting networks. On families it saw, a non-negative linear cost model has a 3.9% median error and within-family Spearman 0.995, beating boosted trees (8.5%). When a whole family is held out, median errors run from 10.5% to 210.7% and the best model changes with the family, but rank agreement stays at Spearman 0.75–1.00. Ordering a 36-design pool by predicted cells×cycles found a design within 2% of the best after 1–5 syntheses against 12.4 (MAC) and 18.6 (FIR) for random order, both optima sitting at an edge of the space, so the test is weak. Stylised: synthesis-only target, no place and route, small designs.

A follow-up to eda-surrogate on its 133 designs in four generator families: when a word-level cell-count surrogate meets a family it has not seen, how many Yosys syntheses of that family restore it? Over 30 random draws per cell, one synthesised design pooled with the other families cuts the linear model’s median error from 48.6% to 18.4% (median over the four families), and training on the new family alone overtakes pooling from about three designs (4.8% against 10.4% at five). Boosted trees need far more (about 12 designs to get under 20%) and pooled boosting is worse than zero-shot on one family for up to five designs. Ranking is good throughout. Stylised: small clean families, random rather than chosen adaptation designs, a synthesis-only target, no place and route.

A follow-up to eda-adapt on the same 133 designs in four generator families. Choosing the k adaptation designs by farthest-point spread in feature space, instead of at random, roughly halves the linear model’s held-out median error at k = 5 (5.3% against 8.5%, new-family weight 5); picking the smallest designs is worst (15.2%). Upweighting the new family’s points helps the linear and ridge models from k = 5 but hurt boosted trees. Stylised: four small clean families, a synthesis-only cell-count target, deterministic choosers scored on different remaining sets, no confidence intervals.

A check on eda-adaptpick, which scored each chooser on the designs it had not chosen. Here each of the four families is split five times into a pool (60%) and a fixed test set (40%); every chooser picks k pool designs from features only and all are scored on the same test set. The spread still beats random draws for the linear model at every k (4.8% against 6.0% at k = 5, weight 5; 2.9% against 5.2% at k = 8) but the margin is 20–45% at 5 to 8 designs, not the earlier halving, and for the linear model it wins in 50–80% of the 20 (family, split) cells rather than all. Picking the smallest designs stays worst. Stylised: 133 small designs, a Yosys cell-count target, no place and route, no significance test.

On the 80-design accelerator table from eda-proposers, a screen that synthesises 4 spread designs, fits a log-linear cell-count model, and then synthesises designs in order of predicted Pareto rank finds 0.990 of the true front’s hypervolume at 12 syntheses (random 0.860, TPE 0.878; 100 seeds) and the whole front on 87% of seeds by 20. The screen reads cycles and error for free, which the baselines do not: with no cell-count model that alone gives 0.908, so the surrogate adds the rest. Stylised: one small smooth space, the surrogate fitted inside one family, no place and route.

The proposers of eda-proposers are shown objectives with Gaussian error (sigma 0 to 0.8 of each objective’s range, fixed per design) and scored on the true objectives, 100 paired seeds. At budget 30 TPE’s gain over random falls from +0.037 to +0.022 (sigma 0.2), +0.013 (0.4) and +0.006 (0.8, interval includes 0). NSGA-II and the genetic method are no better than random from sigma 0.1; annealing is worse than random at every sigma. Stylised: synthetic independent noise, one 80-design table, generic-gate cell counts, no place and route.

The 100-seed proposer runs of eda-proposers re-scored under five hypervolume reference points, front recall, IGD+, an epsilon indicator and log-scaled cell counts. The winner (TPE at budgets 16 and 30) is the same under all of them, but its lead over random at budget 30 shrinks from +0.045 (reference 1.01) to +0.002 (reference 5.0), while recall shows +0.279. At budget 8 the order is decided by annealing and flips with the indicator. Stylised: one 80-design space, generic-gate counts, no place and route.

A follow-up to eda-screen on the same 80-design accelerator table. A random search that uses the free cycles and error objectives (no cell-count model) finds 0.901 of the true front’s hypervolume at 12 syntheses, against 0.860 for plain random, 0.878 for TPE and 0.990 for the 4-fit screen (100 seeds). So +0.041 of the screen’s +0.130 lead comes from the free objectives and +0.089 from the surrogate. The baseline stalls once the free-objective layer is spent and falls below random and TPE by 30 syntheses. Stylised: one 80-design space, generic-gate cell counts, no place and route.

A follow-up to eda-screen and eda-adapt on 100 sampled 27-design spaces of two families (MAC engine, FIR filter). A screen whose cell-count model was trained only on the other families reaches 0.94 to 0.98 of the true front’s hypervolume with 3 Yosys syntheses and about 1.00 by 8, against 0.83 to 0.85 for random search at 8. The cost model’s absolute error is large (median 22–222% for ridge), but its ranking is what the screen uses; refitting on the screen’s own syntheses adds little, and spending the first syntheses on an adaptation spread hurts at tiny budgets. Stylised: tiny fronts (3–5 designs), generic-cell counts, one free objective, no place and route.

All 400 ABC pass sequences (up to three passes of seven) mapped to SKY130 on eight small datapath designs, so every optimum is known. The best recipe differs per design and transfers badly: one design’s best recipe scores a mean 1.31× (worst 2.06×) the other’s optimum, and score rankings of recipes correlate only weakly across designs (Spearman −0.51 to 0.46). A leave-one-out consensus recipe is only slightly better than a median sequence (1.22× against 1.26×), and warm-starting a hill climber with it helps one design (mac4) but is within noise of random search on average at budgets 10 to 40. Stylised: eight hand-picked toy designs, ABC’s static delay, no place and route; the OpenROAD-settings half of the milestone is not done.

Mutation study on the MAC accelerator: 91 compilable mutants (operator, literal, deletion and ROM edits), of which 66 are killable and 16 are proved equivalent by induction. 64 random vectors kill 99% of the killable ones, 16 coverage-directed vectors 97% (16 random: 95%), and bounded Yosys formal checking 71% because 19 SAT runs timed out. Cost per kill: about 1 s for simulation against 52 s for a formal kill. Stylised: one design, one bound, one solver.

Replay of the eda-verify mutation log (91 mutants, 20 seeds), costing each check cascade in CPU seconds. Formal alone takes 16,354 s for 47 kills and 16 equivalence proofs; random simulation first and formal only on the survivors takes about 7,500 s and finds 66 of 66 killable mutants, a 54% saving. The order among the cheap stages changes the total by under 2%; the remaining cost is formal working on equivalent or timed-out mutants, which no ordering removes. Stylised: a re-analysis of one design, one solver and its timeouts; nothing new was simulated.

Replay of the eda-verify mutation log with a time cap on the formal stage. Every formal kill in the log finished within 164 s, while equivalence proofs take about 222 s, so a 170 s cap loses no kill (66 of 66 killable mutants still found) and saves 41% of the cascade's CPU, but gives up all 16 equivalence proofs; a 230 s cap keeps 15 of them and saves 23%. Caps of 30 s or less start losing kills. A cap learned from half the mutants worked on the other half when the training half contained formal kills and failed (1.6 of 29 kills lost) when it contained none. Stylised: one design, one solver, 91 mutants; nothing new was simulated.

Replay of the eda-verify log on the 27 mutants that 16 directed vectors do not kill (16 provably equivalent, 9 timeouts, 2 formal kills). Predicting from the mutated source line and running formal only on predicted-equivalent survivors costs 3,298 CPU-s against 7,414 s for always running formal (−55%) and still finds 14 of 16 proofs, 93% accurate under leave-one-line-out; smoother rules (3-NN, a one-split rule) find 12 of 16 and operator kind is no better than guessing. The signal is the design region the solver finds hard, not a transferable rule. Stylised: 27 mutants, one design, one solver; nothing new was simulated.

Uncertainty for eda-equivpredict, replayed from the same eda-verify log. The 27 survivors sit on only 11 distinct source lines, so a line-cluster bootstrap gives a 95% interval of 76.5–100% around the observed 25 of 27 (92.6%), against a 59.3% majority-class baseline, and a permutation test that shuffles line groups gives p = 0.012. One design, one solver, predictors chosen with the log in view. Stylised.

Follow-up to eda-conefeat on a design the idea was not fit on: a 2×4 systolic array from chip-systolic is mutated, 32 of 143 compiling mutants survive random simulation, and Yosys tries to prove them equivalent (12 proved, 20 timeouts at 60 s/120 s, none killed). An identical post-synthesis cell histogram is always right (3 of 3 across this design and the MAC engine) but finds only 3 of the 28 proved equivalents, so it saves about 3% of formal CPU; equivalent mutants usually change the netlist by −75 to +131 cells, and a zero change is as common among timeouts as among proofs. Two designs, short timeouts on the new one. Stylised.

Follow-up to eda-equivpredict on the same 27 survivors, now with Yosys installed. Position-free features (cell-count change after synthesis, miter size, identical cell histogram) are scored under leave-one-line-out. None beats guessing the majority class (16 of 27, 59.3%); the source-line rule gets 25 of 27. The nine solver timeouts barely change the netlist (|Δcells| 0 for six), but equivalent mutants span 0 to 178, and miter size is nearly constant (1,188–1,199). A negative result on one design; cone depth and fan-in were not tried (see eda-conehash).

The next step eda-conefeat named. Golden and mutant are lowered to gate level without ABC, and each flip-flop and output is compared by a Merkle hash of its fan-in cone. Features of the changed cones (count, gates, depth, leaves, registers reached downstream) are scored under leave-one-line-out on the same 27 survivors. None beats the 59.3% majority class (best 13 of 27). One observation, found after looking at the table: all seven survivors that change exactly one sink are literal edits on two lines, and none is provably equivalent (six of the nine solver timeouts are among them). One design, one solver, stylised.

Same 133 Yosys-synthesised designs in four families, fixed 40% test set per family, new-family weight 5. Over 40 splits × 4 families the paired gap APE(spread) − APE(random) has a 95% bootstrap interval excluding zero for the linear model at k = 2, 3, 5, 8 (median −2.45, −0.71, −1.01, −0.73 points) and for ridge except k = 3, where the spread is worse (+1.00, interval +0.19 to +1.90). The extremes chooser is worse than random at k = 2 to 3. The alu family drives the largest gaps and sorter reverses the sign at k = 3 and 5. The intervals reflect split noise on the same designs, not a population of families, and are narrow for that reason. Inputs are the committed dataset (Yosys 0.33 counts); weights and scaling are untuned defaults.

Same 133 Yosys-synthesised designs in four families as eda-adaptci, whose intervals resampled (family, split) cells that reuse the same designs. Here each bootstrap replicate redraws every family's designs with replacement and recomputes the median paired gap APE(spread) − APE(random) over 160 cells. The spread beats random draws at k = 5 and 8 for linear and ridge (design-level intervals −1.18 to −0.15 and −1.82 to −0.34 at k = 5) and at k = 2 for linear, but the linear k = 3 and ridge k = 2 intervals now include zero, and the ridge k = 3 loss is +1.16 with interval −0.64 to +3.31. Intervals are up to about 2.5 times as wide as the cell bootstrap. Limitations: four hand-written families, ~33 designs each, pool designs not resampled, untuned weights, Yosys cell counts rather than post-route PPA; no input is assumed beyond the committed dataset.

All 133 designs of eda-surrogate (four generator families) are mapped to SKY130 HD with Yosys 0.33 and ABC and placed with the OpenROAD PyPI wheel (placement-based parasitics, repair_timing at 8 ns). The few-shot curves of eda-adapt are refitted to repaired area and to placed period, with the generic cell count as a paired check (it reproduces eda-adapt’s table exactly). With word-level features only, an unseen family’s placed area has a median error of 39% (ridge) or 60% (non-negative linear); one placed design from the new family cuts these to 23% and 27%, and about three reach 20% for most families, the same order as for cell counts. Training on the new family alone overtakes pooling from about three designs; boosted trees need 12 for two families. Period is harder to read: gbr is at 20% with no new design and halves with eight. Limits: placement only (no routing or clock tree), ideal clock, one ABC target, 133 designs from four hand-written generators, no confidence interval over designs; the period target is the placed period of a netlist mapped at a loose 8 ns, not the fastest the design runs.

Extreme-value, sparse, one-hot and mixed input generators, 5,000 vectors each, run against the 26 eda-deepdraw targets (16 proved equivalent, 9 formal timeouts, plus del@122). No generator catches any of them, so none of the 16 equivalence proofs is contradicted, and a bug visible to a given generator among the 9 undecided mutants has per-vector detection probability below 6×10⁻⁴ (95%). The del@122 mutant prints 90 output rows for 100 vectors with no wrong value, confirming truncation. Stylised and negative: one design, hand-chosen generators.

eda-sky130rung mapped each of 40 MAC-engine designs with an unconstrained ABC map, so each ran at its own clock. Here every design is mapped at six shared targets (3–10 ns, map -D T; upsize; dnsize, Yosys 0.33, SKY130 HD tt 25 °C) plus the baseline, 280 mappings. Cell count still ranks area (Spearman 0.995–0.996 at every setting). Logic depth ranks delay at only 0.34–0.82 depending on T, never reliably. No design reaches 3 ns; 6, 15, 25, 39 and 40 of 40 meet 4, 5, 6, 8 and 10 ns. With one shared clock the feasible (area, cycles) front equals the generic front (p8, p4, p2, p1 at 4 bits; p8 drops out at 4 ns), and p4w4 is the best area × latency design at every feasible T, so the front change reported with per-design clocks came from the clocks, not the cell library. Limits: ABC combinational delay only (no wires, clock tree or placement), one family, one recipe, no place and route, so none of it is sign-off or silicon.

A deep random draw on the 26 eda-verify mutants that 64-vector random testing never caught or flagged oddly (16 proved equivalent, 10 formal timeouts). 20,000 further uniform vectors catch none of the 25 survivors, so none contradicts a formal equivalence proof, and a random-visible bug among the 9 undecided mutants has per-vector detection probability below 1.4×10⁻⁴ (95%), sixteen times tighter than before. The one apparent failure, del@122, again fails exactly 10 vectors short of the draw, consistent with truncated output rather than a wrong value (not confirmed). Stylised: one design, uniform random inputs, same vector stream for every mutant.

eda-sky130rung found that generic logic depth ranks SKY130-mapped critical-path delay at only Spearman 0.611 over 40 MAC-engine designs. This project computes cheap delay proxies on the same generic gate netlist (Yosys 0.33 write_json) and ranks them against the mapped delay: weighting gates by type (logical-effort constants from Sutherland, Sproull and Harris 1999) changes nothing (0.609), while adding fan-out lifts agreement to 0.83 (logical effort with real fan-out) and 0.90 (a type-blind fan-out model). Gate count alone reaches 0.911, so on this family delay is largely size. All 200 random re-weightings of gate types beat unit depth (0.667 to 0.911). Replacing the mapped delay by any proxy in area × cycles × delay finds the same best design but misses the 5-bit design the true (area, latency) front gains (3 of 4 front members for every proxy). Limits: one design family, one ABC script, mapped delay from ABC stime without wires or place and route; the 0.5 fan-out coefficient is not sourced; not sign-off.

Detection-probability model of the eda-verify mutation log (91 mutants, 20 seeds). Random vectors catch 41 mutants on the first vector, 24 with a per-vector probability between 0.03 and 0.95, and never catch 25 (16 provably equivalent, 9 formal timeouts). A geometric first-failure model fits the observed miss rate within 0.005 at every budget up to 64 vectors, and predicts 45 vectors for a 1% miss rate and 118 for 0.1% (extrapolated beyond the data). The 1,280 clean vectors bound an undetected bug's per-vector probability below 0.0023 at 95%, so random testing cannot tell a rare bug from an equivalent mutant. Stylised: one design, 91 mutants, a tail set by 2–3 mutants; nothing new was simulated.

A design loop that generates unseen RTL has no trusted reference output, so this project scores five properties that need only the spec's 20-cycle latency and the module's own repeatability on the 91 compilable eda-verify mutants of the MAC engine. They kill 22 of the 66 killable mutants (0.33) and flag none of the 16 proved-equivalent or 9 undecided ones. Every kill is a latency change or hang; all datapath mutants (including all 15 ROM edits) pass, since a wrong value is still timed and repeatable. The 16 coverage-directed vectors with a golden model catch all 22 as well and 40 more, so the golden-free checks add nothing on this design. Preliminary: one design, five author-chosen properties, simulation only; value-level properties and a formal check were not tried.

Using the 40 SKY130-mapped MAC-engine designs of eda-sky130rung as ground truth (Yosys 0.33, ABC dc2; map, SKY130 HD tt 25 °C 1.80 V), three cheap screens rank the designs and only the top k get the expensive mapping. The best design (p = 4 lanes, 4 bits) is first in the generic cells × cycles order for area × cycles, area × latency and latency alike, and fifth for the free analytic model. Over 5,000 random pools of 20 designs, mapping 3 captures the pool's best 0.970 of the time (Wilson 95% 0.965–0.975) against 0.15 for random choice, and 0.987 when logic depth is added, even though depth ranks the mapped delay at only Spearman 0.611. One mapping already lands within 1.078× of the pool optimum on average. Preliminary: one design family, 40 points (the intervals cover only the random draws, not family variation), a synthesis-model truth with no place and route, and counts of mappings rather than seconds. No input is invented: all numbers come from the committed mapped data.

The eda loops score designs with Yosys and ABC only. Here the 40 MAC-engine designs (1–8 lanes, 4–8 bits) are mapped at two shared targets (5 and 8 ns) and then placed with OpenROAD (the pip install openroad wheel: floorplan, placement, placement-based parasitics, repair_timing; SKY130 HD tt 25 °C). ABC area still ranks repaired area (Spearman 0.997–0.999). ABC delay ranks placed delay at 0.61–0.80, and wires add a median 36% to the period (up to 1.99×; worst for 8-lane arrays). At 5 ns none of the 15 designs ABC calls feasible meets timing after placement; at 8 ns, 39 are feasible in ABC, 1 after placement and 27 after repair for 3.5% median area. Where a front exists it is unchanged (p8, p4, p2, p1 at 4 bits) and p4w4 stays best by area × latency. Limits: no routing or clock tree (the wheel's Tcl floorplan and track commands segfault, so placement parasitics are used), ideal clock, repair stops at timing met so repaired periods are capped, one family, one recipe, one utilisation; not sign-off.

The eda projects judge cheap proxies by Spearman rank correlation with the SKY130-mapped objective, but a search loop only uses the top of the proxy's list. Over 207 screens of the 40 MAC-engine designs of eda-sky130rung (7 named proxies from eda-delayproxy and 200 random re-weightings of its logical-effort delay; Yosys 0.33, ABC dc2; map, SKY130 HD), agreement predicts payoff only when the screens already rank well. For mapped area × latency, across screens Spearman agreement and the chance that the pool's best design is among the first mapped correlate at 0.60 (bootstrap 0.50 to 0.68). For mapped latency alone they do not (−0.13, −0.26 to 0.02): the highest-Spearman screen (0.958) maps the best design first only 0.324 of the time, while gate count, at Spearman 0.551, does so 0.692, and 14 of 175 screens with Spearman ≥ 0.9 do not put the true best in their top 3. The best design's rank in the screen's order predicts payoff (0.90 for latency) but a loop cannot compute it without the mapping. The area × latency screens reproduce eda-latencyhalve's 0.636 and 0.970. Preliminary: one design family, one ABC script, no place and route; the swept screens are correlated variants of one model, so the bootstrap over screens is optimistic.

eda-noisy injected synthetic Gaussian error into the objectives a proposer sees. Here the error is measured: on the 40 MAC-engine designs, proposers search generic-gate objectives (cells, cycles, optionally cycles × depth) and are scored on SKY130-mapped area and latency from eda-sky130rung (Yosys 0.33, ABC dc2; map, pinned ORFS commit). The generic views differ from the mapped truth by RMS 0.036 (area) and 0.123 (latency) of each objective’s range, yet searching them costs within ±0.01 of hypervolume against searching the truth, and TPE’s lead over random at budget 20 is unchanged (+0.037, 95% CI +0.032 to +0.042, 200 paired seeds). iid noise at the matched level gives a similar answer; at σ = 0.2 it does cost TPE 0.012. Limits: one toy design family, one ABC script, no place and route (not sign-off), and the error objective is shared by both views.

Using the 133 SKY130 designs placed with OpenROAD in eda-adaptplaced (four generator families), each held-out family is screened for its (repaired area, placed period) Pareto front with area and period cost models trained on the other three families; each placement reveals both objectives and costs one budget unit, 60 random 75% subsets per family. With 3 placements the screen reaches 0.989 of the true front’s hypervolume (pooled over families), 1.000 from 5 to 6, against 0.578 and 0.710 for random search; a screen with no models (a constant guess, random tie-break) is no better than random. A ridge period model is poor on fir (Spearman 0.26) and the screen still works, and giving it no period model at all changes nothing from 2 placements on. The test is easy: area and period both grow with design size, so the true fronts hold only 1.0 to 1.6 designs on average; the screen mostly finds the smallest, fastest design. Preliminary: one ABC target, placement only (no routing), one run per design, no second objective that trades off against area, such as cycles.

The 40 MAC-engine designs of eda-harness (1–8 lanes, 4–8 bits) were mapped to the SKY130 HD standard-cell library (Yosys 0.33, ABC dc2; map, flip-flops mapped with dfflibmap, tt 25 °C 1.80 V liberty at a pinned ORFS commit). Generic-gate cell count ranks mapped area almost perfectly (Spearman 0.995, Kendall 0.954; 6.4–8.4 µm² per generic cell), but logic depth ranks ABC's mapped critical-path delay only at Spearman 0.611. So the (cells, cycles) Pareto front is identical to the (area, cycles) front, yet adding clock period moves it: with latency = cycles × delay, one of four generic-front designs drops off and a 5-bit design joins; top-5 overlap on the combined objective is 0.60. Limits: one design family, one ABC script, unconstrained map delay with no wires or placement, no place and route (not installed), so none of it is sign-off or silicon.

The 10 survivors that Yosys' SAT and induction left undecided (including the known-truncating del@122) were re-checked with yosys-smtbmc and z3. At depth 24 (one inference is 20 cycles) all 10 time out at 900 s; a depth sweep on two targets passes to depth 10 in about 3 s and times out at depth 12 (240 s limit), so the route is no stronger than the built-in SAT at the depth that matters. A pass at depth 10 is not an equivalence claim: the sweep includes a mutant that simulation shows is killable. Negative result: one design, one solver (Yices and Boolector were not installable here), word-level encodings not tried.

chip-systolic ranked 4×C systolic arrays against P-lane MAC engines by generic-gate cells × cycles. Here all 24 designs (word length 4, 6, 8; batch of 4) are mapped to SKY130 HD at six shared targets (3–10 ns, map -D T; upsize; dnsize, Yosys 0.33) plus the unconstrained baseline, 168 mappings. A MAC-lane engine (P=4, 4-bit) has the best area × latency at every feasible target; the best array is 1.61× worse unconstrained and 1.66× worse at 5–10 ns. The shared clock removes many arrays (systolic / lane designs meeting the target of 12 each: 0/3 at 4 ns, 2/7 at 5, 8/12 at 10), and the (area, cycles) front changes with T. Limits: ABC combinational delay only, no wires or place and route, one model, one batch size, one recipe.

Poisson, Murphy, Seeds, Bose-Einstein and negative-binomial yield models, a closed-form dies-per-wafer count checked against an exact grid count, and a chiplet cost model with known-good-die testing and assembly yield. Inputs: CSET's 2020 estimates of TSMC 300 mm wafer prices (9,346 USD at 7 nm, 16,988 USD at 5 nm) and the defect densities TSMC gave in 2020 (0.09 and 0.10–0.11 /cm², via AnandTech). At negative-binomial α = 3 a 600 mm² die yields 61 % and costs 179 USD at 7 nm, 55 % and 359 USD at 5 nm; the choice of yield model moves the 5 nm figure from 328 to 382 USD. The closed-form dies-per-wafer count undercounts square dies by 1–12 % (100 to 800 mm²). Two chiplets beat one die from about 300 mm² of logic at 0.11 /cm² (assembly 30 USD plus 5 per chiplet), from 126 to 728 mm² across the swept defect densities and assembly costs; the yield model moves the crossing by 15 %. The cost CSET quotes for a 600 mm² die is not reproduced (the 5 nm figure is about 238 against 359 here); their die sizes are not known. Assumed, not sourced: the clustering parameter α, the 10 % die-to-die overhead, assembly costs and bond yield (swept). Prices are a 2020 snapshot.

An open research programme; milestone 1 is measured. Over 10 small designs, 60 ABC pass sequences each and two clock targets (1,200 runs through Yosys, ABC and OpenROAD on SKY130 HD), the generic-gate rung's Kendall tau-b against routed (global-route plus timing repair) area × period is below 0.7 on all 9 designs where it is defined (median −0.04), and its pick costs a median 13.5% of routed area × period. The liberty-mapped rung is no better than 0.59 median tau at a tight clock (median regret 10.5%) but nearly exact at a relaxed one (0% regret), because timing repair reorders designs. Routed points cost about 8× a generic point here, so there is little to save on designs this small. Limits: one corner and utilisation, global-route estimates, ten small designs. Milestone 2 replays search on the cached table at equal wall-clock: screening the pool at the generic-gate or mapped rung and verifying the top points does not beat random or hill-climbing search (45 s: regret 1.08% and 1.27% against 0.94% and 0.61%), and loses badly at smaller budgets. Hypotheses H2 to H5 (multi-fidelity wins, coverage, proof prediction) are not yet run. Milestone 3 replays successive halving across the four rungs: starting from the generic-gate rung it is the worst strategy (about 10% mean routed regret at the tight clock at 45 s against 0.94% for random search); starting at the mapped rung wins on most designs at a relaxed clock but loses heavily on two; a 6-point routed pilot that picks the start rung recovers the designs plain halving loses (H3), so there is no multi-fidelity gain at equal wall-clock on this 50-point pool yet. Milestone 4 (H4) replays conformal shortlists: a routed pilot of 10 to 16 points calibrates a one-sided bound on routed area × delay from a cheap rung. On the mapped rung the routed optimum is kept 0.99 of the time at nominal 0.90 (0.90–0.92 at 0.80) while routing 42–57% of the pool, against 0.53–0.65 for random search with equal routed runs; on the generic-gate rung coverage is 0.65 at nominal 0.80, no better than random search, so H4 is refuted there. Limits: 20 groups from 10 small designs, one corner. H5 (milestone 5): across 752 Yosys SAT-miter proofs of ABC rewrites on 15 designs, proof time is set by design size (multiplier median 0.01 s at 4 bits, 11 s at 8, over 10 s at 9–10) and never by a rewrite failing; leave-one-design-out AUC is high pooled (0.96–0.998) only because it reads design size, and within the 8-bit multiplier it is 0.65–0.78 against 0.81 for the rule “the rewrite shrinks the netlist”. One solver, one timeout. Milestone 6 (theory): define a rung’s inversion as the largest log-factor by which it ranks a truly worse candidate at or ahead of a better one; halving’s routed regret is then at most the sum of the cut rungs’ inversions (proved; holds on all 40 table cells). It is vacuous for the generic-gate rung (inversion above 0.3 on 8 of 10 groups) and loose for the mapped rungs (bound 0.23–0.35 against about 0 realised); a 10-point pilot sees a median 52–67% of the inversion but cannot certify it. The probabilistic version is open.