How many SKY130 mappings does a generic-gate screen need to find the best area × latency design?

What it found

Using the 40 SKY130-mapped MAC-engine designs of eda-sky130rung as ground truth (Yosys 0.33, ABC dc2; map, SKY130 HD tt 25 °C 1.80 V), three cheap screens rank the designs and only the top k get the expensive mapping. The best design (p = 4 lanes, 4 bits) is first in the generic cells × cycles order for area × cycles, area × latency and latency alike, and fifth for the free analytic model. Over 5,000 random pools of 20 designs, mapping 3 captures the pool's best 0.970 of the time (Wilson 95% 0.965–0.975) against 0.15 for random choice, and 0.987 when logic depth is added, even though depth ranks the mapped delay at only Spearman 0.611. One mapping already lands within 1.078× of the pool optimum on average. Preliminary: one design family, 40 points (the intervals cover only the random draws, not family variation), a synthesis-model truth with no place and route, and counts of mappings rather than seconds. No input is invented: all numbers come from the committed mapped data.

A figure from its own output

Paper, code and results

• README and method
• Experiments and results
• Code
• Tests

More in Algorithmic chip-design loops

• Does ABC's pre-layout delay and area view of 40 MAC engines survive placement and timing repair on SKY130?The 40 MAC engines placed with the pip OpenROAD wheel: ABC area still ranks placed area (Spearman 0.997+), ABC delay only 0.61 to 0.80, wires add a median 36% to the period, and no design ABC calls feasible at 5 ns meets it after placement.
• Does a cheap rung's rank correlation with the expensive rung predict how well it works as a top-k screen?Across 207 cheap screens of 40 MAC engines, Spearman agreement with SKY130-mapped latency does not predict top-k screening payoff (−0.13 at k = 1): the highest-Spearman screen (0.958) maps the best design first 32% of the time, gate count (0.551) 69%; for area × latency it does (0.60).
• If a design search only sees generic-gate numbers, does it find a worse SKY130 Pareto front?Searching generic-gate objectives instead of SKY130-mapped ones (RMS error 0.036 on area, 0.123 on latency) costs within 0.01 of hypervolume on the 40 MAC-engine designs, and TPE's +0.037 lead over random at budget 20 is unchanged.
• Can a cost model trained on other chip-design families screen a new family's placed area-period Pareto front, even though period is hard to predict?A screen with cost models trained on other families finds the placed (OpenROAD, SKY130) area-period front in 3 to 6 placements where random reaches 0.92 only at 16, but the true fronts hold only 1 to 2 designs, so the test is easy.
• Does generic-gate cell count rank accelerator designs like SKY130-mapped area and clock period?The 40 MAC-engine designs mapped to the SKY130 HD cell library: generic cell count ranks mapped area at Spearman 0.995 but logic depth ranks mapped delay at only 0.611, so the (area, cycles) Pareto front is unchanged while the (area, latency) front loses one design and gains another.
• Can an SMT bounded model check (z3) settle the 10 RTL mutants that Yosys' SAT and induction left undecided?Z3 bounded model checking via yosys-smtbmc decides none of the 10 undecided eda-deepdraw survivors at the 24-cycle depth a full inference needs; its cost passes from about 3 s at depth 10 to over 240 s at depth 12.

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.