Task-specific AI accelerators

A one-hidden-layer MLP on pooled MFCC features of Speech Commands v0.02 (10 keywords plus unknown), quantised to 2–8 bit weights, mapped to a serial-MAC RTL engine that matches an integer NumPy reference bit for bit on all 40 swept configurations. Test accuracy saturates near 75% (0.752 at 128 hidden units, 4 bits); 4-bit weights are within 0.4 points of 8-bit at 64 and 128 units, 2 bits collapses at small width, and a 64-unit 4-bit design (0.722) uses about 31% of the best design’s modelled energy. Modelled classifier energy is 0.0045–0.19 µW at 4 inferences per second, far below the 1.8 mW microphone floor in ambient-wearable. Stylised: assumed 45 nm energy constants not re-checked, generic-gate area without memories, no front end, a third-party dataset mirror, and a weak feature set.

A streaming serial-MAC engine with no weight memory (the host feeds one operand pair per clock over the 16 input pins; hidden activations sit in a rotating shift register), bit- and cycle-exact against an integer reference in Icarus on 32 geometries, synthesised to SKY130 HD with Yosys. Area is 6,300–24,500 µm² (661–2,090 cells) for 8–64 hidden units and 2–8 bit weights; flops are 33–53% of it, and 8-bit weights cost about 3,000 µm² more than 4-bit. Against an assumed 161×112 µm 1x1 tile (18,032 µm²), the best model by accel-kws test accuracy that fits one tile at 70% utilisation is 16 hidden units, 8-bit weights, 120 inputs (0.616); two tiles take 64 units at 4 bits (0.738), a 1.7× area step for 12 points. Stylised: synthesis only (no placement, routing or timing), random weights in the RTL check, accuracies carried over from accel-kws models that were not re-run through this engine, and the tile area is from a search-result snippet of a Tiny Tapeout guide, not the tile table.

Exhaustive joint search over the 40 measured accel-kws keyword-spotting models and six MAC lane counts (240 designs), against a model-first flow, at deadlines of 2,000–20,000 cycles. The most accurate model (validation 0.775, test 0.752) needs 16 lanes at 2,000 cycles and 7,667 generic cells; accepting 2 validation points less (test 0.738) cuts area by 31–42%, and 3 points by 35–56%. Stylised and only partly the milestone: models are a fixed measured table (the dataset was unreachable), cycles for more than one lane are analytic and not RTL-simulated, memory bandwidth is not counted, area is generic gates, and no NSGA-II or Bayesian search was run (the space is small enough to enumerate).

NSGA-II against random sampling, 30 seeds each, on a 3,840-design space (40 measured accel-kws models × 6 lane counts × 4 memory-bank counts × 4 supply levels) under a latency deadline, scored against the exact front from exhaustive search. At 20.8% of the space NSGA-II finds 54% and 89% of the exact front's designs (50 and 200 µs deadlines) against 19% and 21% for random search, yet hypervolume is 0.97–1.00 for both, so random search is already good enough if only a near-front is needed. Stylised: bank and supply models are assumptions and no multi-lane RTL was simulated.

A sweep of NSGA-II population size (10–80), per-gene mutation rate (0.02–0.5) and crossover on the 3,840-design keyword-spotting accelerator space of accel-nsga, at 400 evaluated designs, 30 seeds, scored against the exact front. The earlier setting (population 20, mutation 0.25) was under-tuned: mutation 0.02–0.1 finds about 0.38 of the front at 50 µs (was 0.28) and 0.71–0.77 at 200 µs (was 0.59), against 0.13 and 0.12 for random search. Population 80 with mutation 0.5 is no better than random. Removing crossover changes little. Stylised: one budget, four genes, tuned on the score it is reported with.

Four dataflows (output-, weight-, input-stationary and reduction-tree) of a P-lane MAC array, as schedules walked cycle by cycle on the 40 accel-kws models, with SRAM-access counts that match closed forms exactly and, at P = 1, the measured RTL cycles of accel-kws. At batch 1 output-stationary is best (input-stationary is a median 1.2× to 4.1× worse, falling with lanes); at batch 4 it wins every model while weight-stationary is a median 4.5–9.0× worse through partial-sum traffic. Allowing an activation buffer flips the batch-4 winner to the input-mapped flows at 32 lanes (1.37× better), so the ranking rests on a modelling choice. Stylised: assumed energy constants, a one-cycle register model, no RTL beyond one lane, Timeloop not tried.

A bounded LRU activation buffer of K 8-bit words added to the four accel-dataflow schedules and swept over the 40 accel-kws models at 8, 16 and 32 lanes. At batch 1 output-stationary wins every model at every K. At batch 4 input-stationary first ties or beats it at K = 32, 64 and 128 words (8, 16 and 32 lanes; 10 of 40 models at 8 and 16 lanes, 30 at 32), and no flip occurs for the 2-bit models. If a buffer read costs half an SRAM read instead of a tenth, the flips mostly disappear. Buffer-read energy is assumed and buffer area is not charged. Stylised.

Output-stationary and reduction-tree matrix-vector engines written in Verilog for the two accel-kws layer shapes (64×70 and 11×64), simulated in Icarus Verilog at 1 to 32 lanes. All 36 sweep points are bit-exact against NumPy, and RTL cycles equal the accel-dataflow schedule model plus a constant 2 (3 with a registered adder tree), including ragged last tiles: output-stationary needs 66 cycles against 46 for the reduction tree on the 11-output layer at 16 lanes, and 142 against 194 on the 70-input layer at 32 lanes. Yosys generic-gate area grows faster for the output-stationary engine (11,799 against 8,216 cells at 32 lanes), partly because of its registered output vector. Stylised: batch 1, generic gates not a library, no memories, no timing.

One parameterised Verilog engine implements output- and weight-stationary batched matrix products (P = 8 lanes) for the two accel-kws layer shapes, simulated in Icarus Verilog at batch 1 to 16. All 20 points are bit-exact against NumPy, RTL cycles equal the accel-dataflow schedule model plus a constant 2, and RTL weight and activation fetch counts match the model exactly. Weight-stationary fetches the 4,480 weights of the 64×70 layer once instead of B times at identical cycles, but keeping its partial sums in registers grows the design from 3,024 to 12,284 generic cells (about 192 flops per extra batch element) against a flat ~3,000 for output-stationary. The model's ‘weight-stationary is worst’ ranking came from partial-sum SRAM traffic that this RTL trades for area. Stylised; generic gates, no memories, no energy figures.

Breakeven price ratios solved from the RTL-measured counts of accel-planebatch (P = 8, batch 1 to 16, two accel-kws layers). Register-file weight-stationary beats output-stationary on energy only if an extra flop costs under about 1% of a weight fetch per cycle at B = 4 (2.6×10⁻³ at B = 16), a bar that falls roughly as 1/B unless idle flops are clock-gated. Weight-stationary with partial sums in SRAM wins only if a 24-bit partial-sum access costs under 0.25 to 0.48 of a weight fetch, which looks implausible. Stylised: no energy constant is measured or sourced, so which side real technology falls on is left open.

Takes the breakeven price ratios of accel-fetchprice and prices them with the SKY130 HD liberty file (an idle dfxtp_1 flop costs 46 fJ per cycle, almost all clock-pin power) and the four OpenRAM SRAM macros shipped with OpenROAD-flow-scripts (10 to 90 pJ per access). If one 4-bit weight is fetched per access, weight-stationary wins at most batches; if weights are packed into the SRAM word (0.8 to 2.9 pJ per weight) output-stationary wins at nearly every batch, and weight-stationary with partial sums in SRAM loses in every case since a word holds fewer 24-bit sums than 4-bit weights. Library characterisation values, not measurements; the per-edge versus per-cycle reading of the OpenRAM figure is unresolved.

Follows up accel-pdkprice, where idle flops made weight-stationary (WS) lose to output-stationary (OS) once weights are packed into SRAM words. Reads the idle clock energy of a flop and of an integrated clock gate (ICG) from the SKY130 HD and GF180MCU liberty files: an idle SKY130 dlclkp_1 costs 0.86 of an idle dfxtp_1 (39.7 against 46.4 fJ per cycle), and GF180 gates cost 0.99 to 1.02 of its flops at 3.3 and 5 V in both track heights. One gate shared by G accumulator flops therefore cuts the idle cost about G-fold. With one gate per 24-bit accumulator, WS needs a weight fetch of only 0.08 to 0.9 pJ (ungated: 2.2 to 26 pJ) and beats OS against every packed SKY130 macro in all 64 macro, layer and batch cells but one (an 80-bit macro on the 11×64 layer at B = 16 needs 27 flops per gate). Library characterisation values, a gate-per-group model with the enable logic, area and the register-file read mux unpriced; no RTL built or synthesised.
Stylised.

Writes the register-file weight-stationary (WS) engine of accel-planebatch with clock gates (one per 24-bit accumulator, or one per set of eight) and synthesises it to SKY130 HD with Yosys. All 32 points are bit-exact against NumPy and write exactly as many accumulator bits as the output-stationary engine, confirming the assumption of accel-gatedprice. A gate per set brings the accumulator clock-pin energy to 1.00–1.07× output-stationary (ungated WS: B×), but area falls only 7–18 % against ungated WS, and gated WS is still 1.2× to 5.3× the output-stationary area at batch 2 to 16 because the extra accumulator sets are flops either way. Stylised: synthesis only, no place and route, clock tree or timing; energy is a liberty-based clock-pin model.

Sweeps the lane count P (2 to 16, with a failed attempt at 32) of the four engine modes from accel-gatedrtl on the 64×70 keyword-spotting layer, in RTL simulation and Yosys synthesis to SKY130 HD. All 29 points are bit-exact and write the same accumulator bits in every mode. Accumulator clock-pin energy stays at B× OS for ungated WS and at 1.01 to 1.07× with a gate per set, independent of P; gated WS stays 1.6 to 1.9× OS area at B = 4 (2.9 to 3.0× at B = 8), flat from P = 4. So the earlier conclusion (cheap to clock, not small) is a property of the batch, not the lane count. Stylised: synthesis only, clock-pin energy only; Yosys exceeded 7 GB at P = 32, so wider engines are not covered.

The accumulator read in the engine of accel-gatedrtl indexed the whole accumulator bus with a variable, which Yosys builds as one wide shifter per lane and which stopped accel-gatedlanes at 16 lanes. An AND-OR read mux over the batch sets gives the same cycles, fetches, accumulator writes and flop count, bit-exact against NumPy at all 48 points (P = 2–64, B = 4 and 8), but weight-stationary engines come out 17–28% smaller in SKY130 HD synthesis (output-stationary unchanged). Gated weight-stationary is 1.45–1.50× the output-stationary area at B = 4 and 2.1–2.2× at B = 8, flat in P, against 1.6–1.9× and 2.9–3.0× before; every point now synthesises under the old 7 GB cap. Stylised: synthesis only, one layer shape, random data, clock-pin-only energy; the cause is inferred from the before-and-after effect.

Repeats the accel-gatedprice pricing with the IHP SG13G2 liberty files, which ship ten SRAM macros with separate read and write energies (GF180 has none). An idle IHP flop costs 34 fJ per cycle and an idle clock gate 0.75 of that (0.86 on SKY130, 0.95 on NanGate45); one gate per 24-bit accumulator makes register-file weight-stationary (WS) beat output-stationary (OS) in all 120 layer, batch, macro and packing cells, needing at most 6 flops per gate. Ungated WS also wins 33 of the 60 packed cells, where on SKY130 it lost nearly all of them: a packed IHP weight fetch costs 72 to 497 idle-flop-cycles against 18 to 62 for SKY130’s macros. A units trap (IHP declares 1 µA but its energies are pJ) is checked against C×V². Library characterisation values, not measurements; clock gate priced for idle clock energy only, no RTL built for IHP.
Stylised.

accel-gatedmux found that a variable-index accumulator read made the weight-stationary (WS) engines of accel-gatedrtl 17 to 28 % too large. The batched engine of accel-planebatch has the same index. Rewriting its read as an AND-OR over constant indices and its write as decoded enables, and re-running all 40 points (two accel-kws layers, batch 1 to 16, P = 8), gives bit-exact outputs and identical cycles and fetch counts, with WS area between −3 % and +12 % of the original and no trend in batch (WS/OS cells at B = 4: 1.66 before, 1.62 after). Negative: the earlier verdict stands, because here the accumulators are a Verilog array that Yosys already muxes per entry. Generic-gate cells from one mapper run per point, which moves about 3 % by itself.

The output-stationary (OS) and reduction-tree (RT, RTp) engines of accel-plane for the 64×70 layer, 4-bit weights, at 1 to 32 lanes, through Yosys and nextpnr-ice40 on an iCE40 UP5K (5,280 logic cells, 8 DSP blocks), 3 seeds, with and without DSP mapping. OS at 16 lanes is the fastest design that fits: 10.2 µs per product, 2,942 cells, 27 MHz, against 12.0 µs for RTp at 32 lanes (3,708 cells). Adder trees clock 1.5 to 2× slower than OS, and OS at 32 lanes does not fit. Letting Yosys use the DSP blocks cuts logic by 13 to 41 % but fails to place beyond 8 lanes, as it does not fall back to logic. Stylised: synthesis and place-and-route only, operands from a shift register (no weight memory), no power, no board.

Minimum-mass design of the 2D Q6 cantilever of accel-surrogatelock under a tip-deflection limit, with the 64×8 FE solve as the expensive evaluator and 150 evaluations per run (8 seeds, two limits). Gap to a best-known design at 150 evaluations: random search 14–20 %, an FE-only evolution strategy 6–8 %, a surrogate-assisted loop 2.3–2.8 % with either a float or a 6-bit QAT MLP (not distinguishable at 8 seeds). At 100 evaluations the assisted loops already match the FE-only strategy at 150. 15–21 % of the surrogate's picks broke the limit when the FE solve checked them. Stylised: one 8-variable problem, a weak ES baseline (no CMA-ES or Bayesian optimisation), no confidence intervals.

The 2D cantilever of accel-surrogate2d with a locking-free Q6 (incompatible-modes) element, which is within 0.6 % of Timoshenko theory on a 16×2 mesh where Q4 gives half the deflection. An 8-32-32-1 MLP (float, 6 and 8 bits) imitates it at three mesh sizes. At 64×8 the surrogate adds about 0.5 to 0.8 points to the FE's own 2.3 % error. In a minimum-mass search over 1,000 designs and 15 limits, a screen with no safety margin breaks the limit in 24 to 33 % of cases (FE alone 6.7 %); a 5 to 10 % margin cuts this to 2 to 9 % for about 0.5 to 1.6 % extra mass. Stylised, random-pool screen, 3 seeds, modelled energy.

The cantilever of accel-surrogate meshed as a 2D plane-stress continuum (bilinear quadrilaterals, 32×4 and 64×8 meshes). An 8-32-32-1 MLP imitates each solve and is quantised to 6 and 8 weight bits. With assumed energy constants the FE solve costs 34× (32×4) and 319× (64×8) the 8-bit MLP's energy, so the break-even that failed for the closed-form beam is met. Against a 128×16 reference mesh the 64×8 solve is itself off by a median 9.2 %, the float surrogate by 8.7 % and the 6-bit QAT surrogate by 9.2 %; the surrogate adds little beside the simulator's own error. Limitations: the locking Q4 elements make the simulator inaccurate, two meshes, three seeds, assumed energy model, no RTL. Stylised.

A 8-32-32-1 MLP imitates an Euler-Bernoulli finite-element cantilever with eight section heights. Shear deformation (Timoshenko vs Euler-Bernoulli) moves the tip deflection by a median 0.09 %; the float surrogate's median error is 1.66 %, about 18× larger, and quantisation adds little at 6 bits with quantisation-aware training (1.95 %) but 21 points at 3 bits post-training. Modelled inference is 3.7 nJ at 8 bits against about 407 nJ for the CPU solve, but the break-even is ~1,600 simulator flops, which a closed-form beam does not reach. Stylised: one tiny network, assumed energy constants, no RTL.

Small MLP policies, cloned from a computed-torque controller for a two-link arm with DAgger and quantised to 8 and 4 bits, with inference latency modelled for microcontroller loops and P-lane accelerators (assumed constants) and the closed loop simulated with that latency. Preliminary and mostly negative: the int8 policies track at least 300× worse than the teacher, which itself barely notices a sample of delay, so policy accuracy rather than hardware speed limits control; the deadline model says hardware only matters above about 10 kHz or for larger networks. Stylised; hardware figures are not measured.

The accel-kws serial-MAC engine, wrapped with on-chip weight ROMs and run through Yosys and nextpnr-ice40 for 15 geometries (hidden width 8–128, 2/4/8-bit weights) on the iCE40 UP5K and HX8K, 3 seeds each. All 15 fit: at most 1,138 of the UP5K’s 5,280 logic cells (22%) and 24 of its 30 block RAMs, because Yosys put the weights in block RAM, so logic grows with weight bits rather than width. Post-route Fmax is 15–22 MHz on UP5K and 37–54 MHz on HX8K, so one inference takes 0.04–0.70 ms. Stylised: the weights are random (Speech Commands was unreachable), accuracies are borrowed from accel-kws, and nothing was run on a board or measured for power.

Pruning, int4/int8, ternary and binary variants of a 64-32-10 MLP on scikit-learn's 8×8 digits (a substitute task: Speech Commands was unreachable), with a modelled energy per inference for a zero-skipping serial engine, over 10 splits. Pruning 75% of int8 weights costs 0.2 points and cuts modelled energy to 36% of dense int8; ternary costs 1.4 points and binary 3.0. Within 1–2 points of float32 the cheapest design still has multipliers, because operand reads dominate in the assumed model; multiplier energy must be about 10× the assumed value before dropping it clearly pays. Stylised: assumed 45 nm constants, no RTL or synthesis, no lookup-table variant, toy task.

accel-sparse's 13 designs (pruned and quantised, ternary, binary) re-run on Speech Commands MFCC features of accel-kws (70-64-11 MLP, 5 seeds, same modelled energy). Negative: no multiplier-free design is within 5 points of float32 (ternary is 19 points down, where digits lost under 1); the cheapest design within 2 points is int8 pruned 50% at 69% of dense int8 energy. Stylised: untuned training, one hidden width, assumed 45 nm constants.

A k-means weight-sharing codebook with a per-input product table (no multiplier per weight) against int8 serial MAC engines, on the 64-32-10 digits MLP of accel-sparse, dense and 75% pruned, over 10 splits. Negative: within 2 points of float32 the table engine does not beat int8 (dense: 3.51 nJ for 8 shared values against 3.56 nJ for int8; pruned: 1.55 against 1.51 nJ), and it only looks better against a baseline that rereads activations per weight. An analytic sweep puts the break-even at layers of about 128 outputs or more, and then only if table reads cost a quarter of an array read. Stylised: assumed 45 nm constants, no retraining or RTL, substitute task.

Tests the break-even accel-lut predicted analytically, on trained 64-N-10 digits MLPs (N = 32, 128, 512, 10 splits), with the table engine on the wide layer and an int8 MAC on the 10-output layer. Mostly negative: the best table design is 14% below int8 modelled energy at width 512 only if a table read costs a quarter of an array read per bit (assumed), and 2× or worse at the array-cost read. Accuracy cost of sharing shrinks with width (K = 8: 1.6 points at 32, 0.4 at 512). Stylised, modelled energy, no synthesis.

accel-lut left its shared values untrained. Here the codebook is kept in the loop for 60 epochs (straight-through, k-means re-fit each step) on the same 64-32-10 digits MLP, dense and 75% pruned, over 10 splits. Mixed: in the pruned network 2 shared values go from a 6.5-point to a 1.7-point accuracy drop, and with an assumed cheap table read (0.04 pJ/bit) that is 1.30 nJ against 1.51 nJ for int8; at 0.16 pJ/bit it loses. In the dense network fine-tuning does not help (8 shared values: 3.2 points down against 1.6 without it). Stylised: assumed energy constants, one fine-tuning recipe, no RTL, substitute task.

Both engines for a 64×N dense layer with 4-bit activations and int8 shared weights, written in Verilog, checked bit for bit against an integer NumPy reference, and synthesised with Yosys to generic gates (assumed gate-equivalent weights). Negative and stylised: the table engine keeps one accumulator per output, so its datapath is 2.4× (N=8) to 11.6× (N=128) the MAC engine's and it takes 1.1× to 3.0× the cycles, even though it stores half the weight bits. Random weights, area only, no energy measured.

Track 8 asked whether co-design beats pairing the best model with a generic engine; this project asks a runtime version: does a small model that answers confident clips and escalates unsure ones to a bigger model beat the best single model? It retrains the accel-kws grid (segments 7/12, hidden 8 to 128, weights 2/3/4/8 bits; 40 integer models) on the original Speech Commands v0.02 tarball with its own speaker-disjoint splits (33,895 / 4,084 / 4,509 clips), 5 seeds. Per seed, every ordered small/big pair is a cascade (about 41,000 per seed), escalating when the small model's integer logit margin is below a threshold chosen on validation only. Energy is the classifier's modelled MAC energy (constants checked against Horowitz 2014 in accel-horowitzcheck) plus the escalated fraction of the big model. At validation targets of 0.65 to 0.74 the cheapest cascade uses 0.73 to 0.98 of the cheapest single model's energy (mean ratios 0.82, 0.98, 0.73, 0.77 at 0.65, 0.70, 0.72, 0.74; 0.92 and 0.98 at 0.55 and 0.60 where only some seeds benefit), but its test accuracy is 0.3 to 1.4 points lower (test-set standard error about 0.7 points). The best single model reaches 0.755 test. Limits: classifier energy only; accel-frontend found the MFCC front end draws about 50 times the classifier, which swamps any cascade saving; clips are isolated words, not a stream dominated by silence; modelled, not measured, energy; one hidden layer; unknown class subsampled.

accel-kws claimed the microphone and MFCC front end, not the MAC array, would set the always-on budget but never counted the front end. This project writes a Q15 integer front end (pre-emphasis, Hamming window, 512-point real FFT as a 256-point complex radix-2 FFT, power, the 247 non-zero mel weights of the real filterbank, a table log, a 10-coefficient DCT) with a counter on every multiply, add and 16-bit word moved. One 20 ms frame takes 7,532 multiplies, 11,009 adds and 15,620 words moved, against 5,184 MACs for the 70-64-11 classifier per inference. Streaming (each frame computed once, 50 per second) the front end draws about 54 times the classifier's modelled power at the assumed constants (8 times counting arithmetic only, 23 to 146 times with memory energy a third to triple), and 211 times if all 49 frames are recomputed for each of 4 inferences per second. Decimating by 2 to halve the FFT saves 115,200 multiplies per second, so a filter costing more than 14.4 MACs per output sample loses. The integer path matches a float reference on a noisy tone (within 0.05 with 2 FFT shifts), but with the usual one right shift per stage and a −61 dBFS microphone floor the cepstral error is 0.19 of their spread at −20 dBFS and 0.68 at −50 dBFS; fewer shifts cut it to 0.07 and 0.41 (4 shifts) or 0.02 and 0.21 (2 shifts) but need 17 to 19-bit words at −10 dBFS. Stylised and preliminary: energy constants are typed from memory of Horowitz (2014) at 45 nm and were not re-checked; the fidelity test uses synthetic voiced frames, not Speech Commands (unreachable), so no accuracy impact is measured.

accel-frontend found that fixed per-stage FFT shifts in a 16-bit word either floor quiet speech or overflow loud speech. This project gives the 256-point complex FFT one shared exponent chosen from the data: the block is scaled up to the largest peak a butterfly stage can take (13,573, from the (1 + √2) growth bound) and shifted down by 1 after a stage only when needed. Stored words stay within 16 bits (largest 27,770 over all runs), the butterfly adder needs 17. On the same synthetic voiced frames with a −61 dBFS microphone floor (40 frames per point), cepstral error as a share of cepstral spread is 0.081, 0.060, 0.032 and 0.016 at −60, −50, −40 and −30 dBFS, against 0.715, 0.662, 0.533 and 0.351 for one shift per stage and 0.236, 0.198, 0.120 and 0.051 for a 2-shift schedule that needs 11 to 16-bit adders. At −20 dBFS and above it is about 0.012 to 0.017, no better than fixed schedules that use 18 to 20 bits (0.002 to 0.014): 16-bit rounding sets a floor near 0.01 of the spread. The exponent logic adds 4,608 adds per frame (11,009 to 15,617) and no multiplies, about 0.5% of the front end's modelled energy under accel-frontend's 45 nm constants. Preliminary: those constants were typed from memory of Horowitz (2014) and not re-checked; the audio is synthetic (Speech Commands unreachable), so the metric is cepstral distortion and no keyword accuracy is measured.

free-citeaudit found Horowitz (2014) among the most-repeated unchecked citations. This project reads Fig. 1.1.9 of the paper (45 nm, 0.9 V) and compares it with every top-level E_* constant in research/accel-*/src: all 34 with a counterpart are within 4% (the 24-bit add is 0.963 of a log-log interpolation, the 0.16 pJ/bit array read is 1.024 times 10 pJ per 64 bits); one constant, a gating energy, has none. The figure's multiplier energy has a width slope of 1.98 (so the repository's bits-squared rule is right) and its add slope is 0.87. What the repository did not model is array size: the figure's read energy grows with a slope near 0.5 against size, while accel-kws charges a flat 0.16 pJ/bit. Re-costing its 40 designs (reads are 90 to 93% of modelled energy) with the size law, extrapolated below 8 KB where the paper has no point, gives 0.23 to 0.81 of the as-built energy, a rank correlation of 0.991 and 17 of 18 front members kept; clamping at the 8 KB point instead gives 0.98 to 1.18 and the same front. Limitations: a processor-cache table, not a weight memory; the sub-8 KB law is an extrapolation; only accel-kws was re-costed; the figure was read from a third-party copy.

accel-lut found a product-table engine loses to an int8 MAC engine (about 2.7× the energy within a 2-point accuracy drop) while charging every array a flat 0.16 pJ/bit. accel-horowitzcheck showed that flat read ignores array size. This project prices each array (weights or indices, activation buffer, the 32-byte product table) as (10 pJ/64) (size/8 KB)α per bit, keeping accel-lut's accuracy and nonzero counts. The cheapest design within tolerance ties the MAC at α = 0.26 (dense) and 0.28 (75% pruned); at α = 0.5, the slope of Horowitz's Fig. 1.1.9 between 8 and 32 KB, it uses 0.52 and 0.68 of the MAC's energy. Every array here is below 8 KB, where the paper has no data, so α is swept rather than chosen and the flip is conditional; a model that never prices arrays below the 8 KB point reproduces the original negative result. Next step: measure small arrays in an open PDK.

accel-pdkprice read the clk0 internal_power of four OpenRAM SRAM macros as pJ per access. Reading the generator source at a pinned commit (five tested facts) shows the value is an average power in mW over exactly one clock cycle, so the access energy is the value times the characterisation period T, which the shipped files do not give (their minimum_period reads 0.09 to 0.1 ns, not usable). Sweeping T = 0.1 to 20 ns over the 64 cells of accel-pdkprice (it reproduces all 64 verdicts at 1 ns): with one weight per access, register-file weight-stationary beats output-stationary in all 32 cells from 3 ns up; with weights packed it wins 0 of 32 at 0.5 ns, 6 at 2, 17 at 5 and 29 at 20 ns (flip periods 0.8 to 31 ns). Partial sums in SRAM lose at every T because the scale cancels. Library values read from source, not a measurement; T is swept, not sourced, because no file gives it; the shipped libraries may predate the pinned source.

accel-cascade found two-stage cascades cut classifier energy by up to 28% but said the saving would vanish next to the MFCC front end. This project computes it by joining that project's committed per-design energies and accuracies (5 seeds, 40 models each) with accel-frontend's 46.77 nJ per frame, at 50 frames and 4 decisions per second (584.6 nJ per decision). The cascades' whole-system saving is at most 0.42% (mean over seeds, accuracy targets 0.50 to 0.74), with 0.3 to 1.4 points of test accuracy lost; the front end must get about 10 to 30 times cheaper before cascades reach a few per cent, and 100 times cheaper for up to 17%. In the other direction, the model with the best validation accuracy (test 0.747 to 0.758) draws 23 to 26 times the cheapest model above 0.5 validation accuracy (test 0.47 to 0.49) in the classifier, but only 5.2 to 5.8% more in the whole system. Modelled energy from accel-kws constants (checked against Horowitz 2014 within 4% in accel-horowitzcheck); the front-end scale factors are a sweep; accuracies are from float features, not the integer front end; nothing is retrained or measured.

accel-ttsizes stopped its sweep at H = 64 so larger tiles had nothing to hold. This project synthesises the same streaming engine at H = 96, 128, 192 and 256 (weights of 2, 3, 4 and 8 bits, 70 and 120 inputs, 64 synthesis runs with the RTL checked against the integer reference in Icarus Verilog) and finds the smallest of Tiny Tapeout's 12 real tile sizes that holds each at 100, 70 and 50% utilisation. Area is roughly linear at about 250 µm² per hidden unit (H = 128: 36,411–40,747 µm²; H = 256: 68,606–72,897). The most accurate model, H = 128 with 4-bit weights (0.752, from accel-kws, which had trained it), needs a 2x2 tile; the best 1x2 model (H = 64, 0.737) is 0.015 less accurate, and a 2x2 is 2.08× the area of a 1x2. A 24-bit accumulator adds 0.1–2.1% area. At H = 256 with 8-bit weights, a random model overflows the 20-bit accumulator, so larger models need a wider one or a trained-model check. Utilisation is assumed, area is synthesis-only, and accuracy above H = 64 was not retrained here (the dataset host was unreachable) and has not been checked against the tile's bias and accumulator limits.

All 96 retrained accel-kws models (70 and 120 inputs, hidden width 8–64, 2–8-bit weights, 3 seeds) on Speech Commands stay inside the streaming engine's limits: the largest layer-1 bias is 43% of the 16-bit limit and the largest accumulator 30% of the 20-bit limit, with no overflow on train or test clips. Accuracy through the tile's wrapping contract equals the integer reference on every model, and the 32 trained seed-0 models run bit-exact (class and cycles) through the Icarus RTL on 30 clips each. The accuracies accel-ttfit used are reproduced to within 0.010 for 3-, 4- and 8-bit weights. Stylised: one hidden layer, weak features, synthesis-only area.

accel-ttfit assumed a 161 × 112 µm tile from a search snippet. This project fetches Tiny Tapeout's own SKY130 tile table (1x1 = 17,955 µm², 0.43% smaller) and re-fits the synthesised keyword-spotting engine (6,300–24,500 µm²) with the retrained accuracies of accel-ttretrain over all 12 tile sizes at 100, 70 and 50% utilisation. One 1x1 tile: the best model is unchanged at 100% (H = 32, 8-bit, 0.693) and 50% (H = 16, 3-bit, 0.563) and flips at 70% (H = 16, 4-bit, 0.596, because the 8-bit model misses by 29 µm²). A 1x2 tile holds H = 64 with 8-bit weights (0.737), the largest model swept. Utilisation is assumed, area is synthesis-only, accuracy is on a substitute feature set; the tile table itself is sourced.