Under a latency deadline, how much engine area does picking the most accurate model first cost, compared with choosing model and lane count together?

research/accel-codesign

Model-first vs joint choice of model and MAC lane count under a latency deadline, on the 40 measured accel-kws models; accepting 2 validation points less cuts engine area 31–42% (stylised, table-based, cycles for more than one lane analytic).

6 tests

What it found

Exhaustive joint search over the 40 measured accel-kws keyword-spotting models and six MAC lane counts (240 designs), against a model-first flow, at deadlines of 2,000–20,000 cycles. The most accurate model (validation 0.775, test 0.752) needs 16 lanes at 2,000 cycles and 7,667 generic cells; accepting 2 validation points less (test 0.738) cuts area by 31–42%, and 3 points by 35–56%. Stylised and only partly the milestone: models are a fixed measured table (the dataset was unreachable), cycles for more than one lane are analytic and not RTL-simulated, memory bandwidth is not counted, area is generic gates, and no NSGA-II or Bayesian search was run (the space is small enough to enumerate).

A figure from its own output

Figure produced by research/accel-codesign: front — accel-codesign/experiments/front.png, written by the project's own experiment code.

Paper, code and results

More in Task-specific AI accelerators

Does NSGA-II find a keyword-spotting accelerator's Pareto front faster than random search at equal budgets?NSGA-II against random search at equal budgets on a 3,840-design keyword-spotting accelerator space with exact ground truth; NSGA-II finds 54 to 89% of the exact front at 20.8% of the space against 19 to 21% for random search, though hypervolume is 0.97 to 1.00 for both. Stylised.
Was accel-nsga's NSGA-II win a tuning accident? Does population size, mutation rate or crossover change how much of the exact front it finds?Sweeps NSGA-II's population, mutation rate and crossover on the accel-nsga space; mutation 0.02 to 0.1 finds about 0.38 and 0.71 to 0.77 of the exact front at 400 designs, against 0.28 and 0.59 at accel-nsga's setting and 0.13 and 0.12 for random search (stylised).
Which dataflow should a small keyword-spotting accelerator use, and does the answer survive allowing an input buffer?Weight-, output-, input-stationary and reduction-tree dataflows of a P-lane MAC array on the 40 accel-kws models, from a cycle-by-cycle schedule simulator that matches closed forms exactly and the P = 1 RTL cycles; output-stationary wins on SRAM energy at batch 4 until an input buffer is allowed, then input-mapped flows win at 32 lanes (stylised, assumed energy constants, no RTL for more than one lane).
How large must an activation buffer be before the best dataflow for a small keyword-spotting accelerator changes?How large a bounded LRU activation buffer must be before output-stationary stops being the best dataflow for the 40 accel-kws models at batch 4: 32, 64 and 128 words at 8, 16 and 32 lanes (for 10 to 30 of 40 models, input-stationary wins), and not at all at batch 1; buffer-read energy is assumed and no area is charged (stylised).
Does a loop-nest cycle model of a P-lane MAC array match RTL at more than one lane, tails included?P-lane output-stationary and reduction-tree matrix-vector engines in Verilog, bit-exact against NumPy at 1 to 32 lanes, with RTL cycles equal to accel-dataflow's schedule model plus a constant 2 or 3 at every point, tails included (stylised, generic-gate area, batch 1, no memories).
Does the weight-stationary advantage in the dataflow model survive RTL at batch above 1, and what does it cost in gates?Output- and weight-stationary batched RTL engines at batch 1 to 16: bit-exact, cycles and operand-fetch counts equal accel-dataflow's schedule model, and weight-stationary's saved weight fetches cost up to 4x the generic gates (stylised, P = 8, no memories).

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Proper scoring & elicitation28 Effort & peer prediction9 Verification games & slashing19 Detection & tolerances14 Markets as routers13 Prediction-market design9 Paying contributors8 Decentralised training systems23 Digital twins & sim-to-real164 LLM chip design loops40 Robot manufacturing loops53 Ambient AI assistant46 Self-replicating manufacturing34 Simulation-first design64 Engineered clothing45 Task-specific AI accelerators40 Algorithmic chip-design loops42 Open-source purpose-built robots44 The software-engineering loop43 Adversarial human imitation41 Open-source residential construction41 Autonomous multi-angle capture34 Sensing, imaging and 3D31 Energy supply and dense energy storage39 Robot societies among people31 Agentic co-design of low-cost robots27 Laundry-hanging robots25 Machine learning on qualitative data23 Robots on the building site27 Civilizations & group psychology1 History & human sciences1

Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.