Does a loop-nest cycle model of a P-lane MAC array match RTL at more than one lane, tails included?

research/accel-plane

P-lane output-stationary and reduction-tree matrix-vector engines in Verilog, bit-exact against NumPy at 1 to 32 lanes, with RTL cycles equal to accel-dataflow's schedule model plus a constant 2 or 3 at every point, tails included (stylised, generic-gate area, batch 1, no memories).

6 tests

What it found

Output-stationary and reduction-tree matrix-vector engines written in Verilog for the two accel-kws layer shapes (64×70 and 11×64), simulated in Icarus Verilog at 1 to 32 lanes. All 36 sweep points are bit-exact against NumPy, and RTL cycles equal the accel-dataflow schedule model plus a constant 2 (3 with a registered adder tree), including ragged last tiles: output-stationary needs 66 cycles against 46 for the reduction tree on the 11-output layer at 16 lanes, and 142 against 194 on the 70-input layer at 32 lanes. Yosys generic-gate area grows faster for the output-stationary engine (11,799 against 8,216 cells at 32 lanes), partly because of its registered output vector. Stylised: batch 1, generic gates not a library, no memories, no timing.

A figure from its own output

Figure produced by research/accel-plane: plane — accel-plane/experiments/plane.png, written by the project's own experiment code.

Paper, code and results

More in Task-specific AI accelerators

Does the weight-stationary advantage in the dataflow model survive RTL at batch above 1, and what does it cost in gates?Output- and weight-stationary batched RTL engines at batch 1 to 16: bit-exact, cycles and operand-fetch counts equal accel-dataflow's schedule model, and weight-stationary's saved weight fetches cost up to 4x the generic gates (stylised, P = 8, no memories).
How cheap must idle flops be, relative to a weight fetch, for register-file weight-stationary to beat output-stationary?Breakeven price ratios from accel-planebatch's RTL counts: register-file weight-stationary beats output-stationary only if an idle flop costs under ~1% of a weight fetch per cycle at batch 4 (falling ~1/B); no energy constant measured (stylised).
At SKY130's own energy prices, does register-file weight-stationary scheduling beat output-stationary?Places accel-fetchprice's breakevens against SKY130 liberty energies (idle flop 46 fJ per cycle; OpenRAM macro 10 to 90 pJ per access): with weights packed into SRAM words register-file weight-stationary loses to output-stationary at nearly every batch; partial sums in SRAM lose everywhere. Library values, not measurements.
Does clock-gating the extra accumulators make register-file weight-stationary scheduling beat output-stationary?Prices clock-gated register-file weight-stationary scheduling from SKY130 and GF180 liberty files: an idle clock gate costs 0.86 of an idle flop (SKY130; 0.99 to 1.02 in GF180), so one gate per 24-bit accumulator cuts the idle cost about 28-fold and flips register-file WS from losing to winning against packed SRAM weight fetches in 35 of 64 cells, in all but one cell at 24 flops per gate. Library values, not measurements.
Does the clock-gated weight-stationary engine hold up once it is written in RTL and synthesised?The clock-gated register-file weight-stationary engine in RTL and SKY130 synthesis: bit-exact, same accumulator writes as output-stationary, clock-pin energy 1.0 to 1.07x OS with a gate per set, but area only 7 to 18 % below ungated WS and 1.2 to 5.3x OS (stylised).
Does the gated weight-stationary engine's verdict depend on how many lanes it has?The gated weight-stationary engine's lane count swept from 2 to 16 (32 ran out of synthesis memory): bit-exact, clock-pin energy 1.01 to 1.07x OS with a gate per set at every P, area 1.6 to 1.9x OS at B = 4 and flat from P = 4, so the verdict depends on the batch, not the lanes (stylised).

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.