Does clock-gating the extra accumulators make register-file weight-stationary scheduling beat output-stationary?
research/accel-gatedprice
Prices clock-gated register-file weight-stationary scheduling from SKY130 and GF180 liberty files: an idle clock gate costs 0.86 of an idle flop (SKY130; 0.99 to 1.02 in GF180), so one gate per 24-bit accumulator cuts the idle cost about 28-fold and flips register-file WS from losing to winning against packed SRAM weight fetches in 35 of 64 cells, in all but one cell at 24 flops per gate. Library values, not measurements.
What it found
Follows up accel-pdkprice, where idle flops made weight-stationary (WS) lose to output-stationary (OS) once weights are packed into SRAM words. Reads the idle clock energy of a flop and of an integrated clock gate (ICG) from the SKY130 HD and GF180MCU liberty files: an idle SKY130 dlclkp_1 costs 0.86 of an idle dfxtp_1 (39.7 against 46.4 fJ per cycle), and GF180 gates cost 0.99 to 1.02 of its flops at 3.3 and 5 V in both track heights. One gate shared by G accumulator flops therefore cuts the idle cost about G-fold. With one gate per 24-bit accumulator, WS needs a weight fetch of only 0.08 to 0.9 pJ (ungated: 2.2 to 26 pJ) and beats OS against every packed SKY130 macro in all 64 macro, layer and batch cells but one (an 80-bit macro on the 11×64 layer at B = 16 needs 27 flops per gate). Library characterisation values, a gate-per-group model with the enable logic, area and the register-file read mux unpriced; no RTL built or synthesised.
Stylised.
A figure from its own output
Paper, code and results
More in Task-specific AI accelerators
- Does the clock-gated weight-stationary engine hold up once it is written in RTL and synthesised?The clock-gated register-file weight-stationary engine in RTL and SKY130 synthesis: bit-exact, same accumulator writes as output-stationary, clock-pin energy 1.0 to 1.07x OS with a gate per set, but area only 7 to 18 % below ungated WS and 1.2 to 5.3x OS (stylised).
- Does the gated weight-stationary engine's verdict depend on how many lanes it has?The gated weight-stationary engine's lane count swept from 2 to 16 (32 ran out of synthesis memory): bit-exact, clock-pin energy 1.01 to 1.07x OS with a gate per set at every P, area 1.6 to 1.9x OS at B = 4 and flat from P = 4, so the verdict depends on the batch, not the lanes (stylised).
- Why did the gated weight-stationary engine need so much synthesis memory, and does fixing it change its area verdict?Why the gated weight-stationary engine needed so much synthesis memory: one variable-index read of the accumulator bus; an AND-OR read mux gives bit-exact, same-cycle engines 17 to 28 % smaller, gated WS 1.5x OS area at B = 4 and 2.2x at B = 8 (was 1.6 to 1.9x and 2.9 to 3.0x), and lets P = 64 synthesise (stylised).
- Does clock-gated weight-stationary scheduling still beat output-stationary on a second open process, with that process's own SRAM?Second-node verdict for clock-gated register-file weight-stationary scheduling from IHP SG13G2 liberty files (idle flop 34 fJ, clock gate 0.75 of a flop, ten SRAM macros with separate read energies): one gate per accumulator makes WS beat OS in all 120 cells, but ungated WS also wins 33 of 60 packed cells because IHP's SRAM costs 72 to 497 flop-cycles per weight against SKY130's 18 to 62. Library values, not measurements.
- Does the accumulator-read bug found in accel-gatedmux also inflate accel-planebatch's weight-stationary area?Does
accel-gatedmux's accumulator-read bug also inflateaccel-planebatch's WS area? No: the rewritten engine is bit-exact with identical counts and its area is within -3 % to +12 % with no trend (WS/OS 1.62 vs 1.66 at B = 4); the earlier verdict stands. - How many MAC lanes of a keyword-spotting matrix engine fit on a small open-toolchain FPGA, and which dataflow is fastest there?Accel-plane's output-stationary and reduction-tree engines at 1 to 32 lanes through Yosys and nextpnr-ice40 on an iCE40 UP5K: output-stationary at 16 lanes is fastest that fits (10.2 us per 64x70 product, 2,942 of 5,280 cells); DSP mapping cuts logic 13 to 41% but fails to place beyond 8 lanes. Stylised, synthesis only.
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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.