Does clock-gated weight-stationary scheduling still beat output-stationary on a second open process, with that process's own SRAM?

research/accel-ihpprice

Second-node verdict for clock-gated register-file weight-stationary scheduling from IHP SG13G2 liberty files (idle flop 34 fJ, clock gate 0.75 of a flop, ten SRAM macros with separate read energies): one gate per accumulator makes WS beat OS in all 120 cells, but ungated WS also wins 33 of 60 packed cells because IHP's SRAM costs 72 to 497 flop-cycles per weight against SKY130's 18 to 62. Library values, not measurements.

8 tests

What it found

Repeats the accel-gatedprice pricing with the IHP SG13G2 liberty files, which ship ten SRAM macros with separate read and write energies (GF180 has none). An idle IHP flop costs 34 fJ per cycle and an idle clock gate 0.75 of that (0.86 on SKY130, 0.95 on NanGate45); one gate per 24-bit accumulator makes register-file weight-stationary (WS) beat output-stationary (OS) in all 120 layer, batch, macro and packing cells, needing at most 6 flops per gate. Ungated WS also wins 33 of the 60 packed cells, where on SKY130 it lost nearly all of them: a packed IHP weight fetch costs 72 to 497 idle-flop-cycles against 18 to 62 for SKY130’s macros. A units trap (IHP declares 1 µA but its energies are pJ) is checked against C×V². Library characterisation values, not measurements; clock gate priced for idle clock energy only, no RTL built for IHP.
Stylised.

A figure from its own output

Figure produced by research/accel-ihpprice: thresholds — accel-ihpprice/experiments/thresholds.svg, written by the project's own experiment code.

Paper, code and results

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.