How many MAC lanes of a keyword-spotting matrix engine fit on a small open-toolchain FPGA, and which dataflow is fastest there?

research/accel-planefpga

Accel-plane's output-stationary and reduction-tree engines at 1 to 32 lanes through Yosys and nextpnr-ice40 on an iCE40 UP5K: output-stationary at 16 lanes is fastest that fits (10.2 us per 64x70 product, 2,942 of 5,280 cells); DSP mapping cuts logic 13 to 41% but fails to place beyond 8 lanes. Stylised, synthesis only.

5 tests

What it found

The output-stationary (OS) and reduction-tree (RT, RTp) engines of accel-plane for the 64×70 layer, 4-bit weights, at 1 to 32 lanes, through Yosys and nextpnr-ice40 on an iCE40 UP5K (5,280 logic cells, 8 DSP blocks), 3 seeds, with and without DSP mapping. OS at 16 lanes is the fastest design that fits: 10.2 µs per product, 2,942 cells, 27 MHz, against 12.0 µs for RTp at 32 lanes (3,708 cells). Adder trees clock 1.5 to 2× slower than OS, and OS at 32 lanes does not fit. Letting Yosys use the DSP blocks cuts logic by 13 to 41 % but fails to place beyond 8 lanes, as it does not fall back to logic. Stylised: synthesis and place-and-route only, operands from a shift register (no weight memory), no power, no board.

A figure from its own output

Figure produced by research/accel-planefpga: latency_vs_cells — accel-planefpga/experiments/latency_vs_cells.svg, written by the project's own experiment code.

Paper, code and results

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.