LLM chip design loops

Installs Yosys, Icarus Verilog and Verilator, records versions, and synthesises adders, a multiplier and a FIFO to a generic gate library: a ripple-carry adder is 5W−3 gates deep 2W−1, and the operator form + gets the same depth with a few more gates. A SAT miter proves the two adders equivalent and rejects a deliberately broken one. Stylised: gate counts, not silicon area; OpenROAD and a PDK are not yet part of the flow.

A harness (a proposer writes Verilog; lint, random-vector simulation and a Yosys equivalence proof score it) with 12 small tasks. One attempt per task written by the session agent (not an LLM benchmark) passed every stage at round 0, so the loop never had a failure to use. Of 414 single-point mutants of those designs, lint rejects 56, simulation 303 and only the formal proof 30 (7.7% of the 389 rejected), while 25 pass everything. A no-LLM random-mutation repair baseline fixes 11/36 broken designs within 4 proposals and 22/36 within 16. Toy: tiny modules, bounded 10-cycle proof for sequential tasks, syntactic mutants.

A checker (Verilator lint, Icarus lockstep simulation against a golden model, Yosys SAT proof for combinational tasks) scores nine small tasks. With the session itself as proposer, 6 of 9 pass from the spec alone and all 9 after one round of mismatch feedback; the three failures were a Gray encoder written as a decoder, a logical shift on a signed value and a combinational pulse that should be registered. Anecdotal: one attempt per round, one proposer who also wrote the tasks, no resampling baseline, simulation only for sequential tasks. Not an LLM benchmark.

A companion to chip-rtl-loop: a four-stage checker (compile, lint, simulation, SAT miter) over ten small Verilog tasks, with a random-mutation hill-climbing baseline that uses no model. Given 1, 2 or 3 injected faults and 60 checker evaluations, the baseline repairs 9/20, 4/20 and 4/20 cases. The session agent (Claude) passed all ten tasks on its first attempt, so the feedback rounds were never exercised and no pass-rate-versus-rounds curve is reported. Preliminary: tiny tasks, one attempt, mutation faults unlike a language model's mistakes, and the optional API proposer is untested.

A loop in which rewrites of a 16-bit adder and a 6×6 multiplier must be proved equivalent to the reference by a Yosys miter before a generic-gate ABC script scores cells and depth. With nine attempts written by the session agent (not an LLM benchmark; two were seeded faults the gate rejected), the best adder is a 4-bit carry-select at 0.85× the reference cells×depth, the same circuit family as the best config of a no-model parameter sweep, so a random sweep of the same budget never beats it (ties in 63 of 200 seeds). No multiplier rewrite beat a * b. Stylised: gate counts, not layout; one tool version; two designs.

Seven behavioural blocks synthesised by Yosys 0.33 to generic gates at widths 4–64. Cell counts for the adder, comparator, equality and 4:1 mux are close to linear in width (fitted exponent 1.00–1.13); the multiplier is quadratic (2.19 overall, 2.06 on the largest widths); the barrel shifter sits at 1.27–1.35. Logic depth scales differently from cells: the default-script adder's depth grows about 2×W (7 to 125) while the comparator's grows slowly (5 to 16). Preliminary: five widths, one tool version, generic gates rather than library area, no confidence intervals.

For every 8-bit constant K (1–255), an 8-bit input is multiplied three ways — the * operator, binary shift-add, and canonical-signed-digit (CSD) shift-add/subtract — and scored by Yosys 0.33 in generic gates; every variant is proved equivalent to the operator form by a miter. The operator tracks binary shift-add (cells correlate 0.97 with the number of set bits of K, 0.65 with CSD digits). CSD uses 75.7 mean cells against 112.9 for the operator (33.0% fewer; fewer cells for 230 of 255 constants, worse for 14) at similar mean depth (20.0 vs 19.6); K=255 drops from 222 to 30 cells. Preliminary: one tool version, one ABC script, generic gates rather than library area, one input width, no shared sub-sums across constants.

A follow-up to chip-constmul: one 8-bit input feeds a bank of M random 8-bit constants (M = 2, 4, 8, 16; 40 banks each), written three ways — the * operator, per-constant canonical-signed-digit (CSD) shift-add, and a greedy shared-sub-sum (MCM) form — scored by Yosys 0.33 in generic gates, every variant proved equivalent to the operator form. Sharing uses 9% fewer cells than per-constant CSD at M = 2 and about 20% fewer at M = 8 and 16 (690 vs 866 at M = 16; 43% fewer than the operator), fewer in 130 of 160 banks and more in 2. Adders removed in the source predict cells saved (Pearson 0.875, about 15 cells per adder). Sharing also recovers the depth CSD loses on large banks (28.2 vs 33.2 at M = 16). Preliminary: random rather than trained weights, one greedy heuristic, one tool version, generic gates rather than library area.

chip-exact4 found Yosys/ABC about 1.2 gates above the proven minimum on isolated 4-input functions. Here every gate of six small netlists (adder, multiplier, comparator, popcount, shifter, priority encoder) under five ABC flows is checked against that exact minimum over all its 4-leaf cuts, counting only logic a local replacement could delete. The disjoint headroom is 0 gates in 28 of 30 runs and 1 gate in the other two, even though the default script cuts 25–42% of the gates of plain mapping on add16 and prio16: the flow’s gains are not local, so an exact small-cone rewrite proposer would find almost nothing. Stylised: six blocks, gate count with free inverters, one Yosys build; replacement circuits were not constructed.

The exact minimum 2-input gate count of every 4-input Boolean function (222 NPN classes, by SAT) against what Yosys/ABC returns on 884 sampled functions. The default flow is exactly optimal on only 34% and averages 1.19 gates above the minimum (max 4); the best of seven scripts per function reaches 38%. A heavier resyn2 script is worse (1.72), and the count changes with which negated or permuted form of the same function is synthesised. One Yosys version, generic gates, 4 inputs only. Preliminary.

A follow-up to chip-ppa-loop: five ABC scripts are applied to five written 16-bit adder structures and eight 6×6 multiplier structures, each proved equivalent to its reference by a Yosys miter. For the adder, cells×depth moves by up to 1.75× with the script for one structure and 1.18–1.94× across structures for a fixed script; the best pair is 0.48× the default-script plain adder. All eight multiplier structures score identically under each script, yet the script alone moves them by 1.17×. Stylised: two designs, one Yosys version, generic-gate counts rather than layout.

Provably equivalent rewrites of generated adder and multiplier RTL (random wire names, shuffled statements, shuffled order of added operands; 864 scored variants, every text proved equivalent to its reference) are scored under three ABC scripts. Names and statement order never change cells×depth. Operand order changes one carry-select adder by up to 1.43× within a script, and its best variant under dch is 17% better than the best adder chip-abc-sweep reported, so that earlier best was one draw from a distribution the text controls. Five other structures are unaffected. Stylised: two designs, one Yosys version, 12 seeds, generic-gate counts, cause not yet traced.

A follow-up to chip-abc-orderpass, which only ran uniform orders. 400 random mixed variants of a 16-bit carry-select adder (each of the 7 a + b + const chains in its own random operand order; all proved equivalent to the reference) are scored under three ABC scripts. The set of blocks whose two chains both start with a, b predicts the Yosys adder count after opt in 400 of 400 variants and fixes the cells × depth: all 8 possible sets occurred, and each had exactly one score per script. The effect is not additive: sharing only block 1 costs 1.38× under dch_map, only block 3 costs 1.00×. Stylised: one adder, Yosys 0.33, a generic-gate library, no place and route.

A follow-up to chip-abc-order. All 36 operand orders of a 16-bit carry-select adder's a + b + const chains (each proved equivalent to the reference) are run through synth one pass at a time. The cell counts first diverge in opt_merge: when a block's two sums both start with a and b, one shared a + b is kept (7 adders instead of 10), which happens in 4 of 36 orders. Cells×depth then takes only two values per ABC script, and the shared netlist is 1.20–1.28× larger under dch_map and resyn2_map but 0.92× under Yosys's default script. Removing opt_merge does not remove the dependence: the spread over orders widens to 1.44–3.17×. Stylised: one adder, Yosys 0.33, generic-gate cells×depth, no place and route.

Eleven small adder-shaped designs whose outputs all contain a + b are written once so opt_merge shares the sum and once so it cannot (each pair proved equivalent). Scored under five ABC scripts, sharing gives fewer cells in 54 of 55 pairs (median ratio 0.76–0.85), but is deeper in 6–9 of 11 designs, so cells × depth favours it in 7–9 of 11. The sign flip seen on the 16-bit carry-select adder in chip-abc-orderpass does not appear. Stylised: generic gates, Yosys 0.33, no place and route.

Six equivalent 16-bit adder styles (each proved against a + b with a Yosys miter) are scored with three ABC scripts. Writing the shared sum by hand (p = a + b, y = p + 1) or as an incrementer (y = x + 1) gives exactly the netlist opt_merge finds for the plain a + b + 0 / a + b + 1 text (cells×depth 2090 / 1232 / 1665), so a hand common-subexpression rewrite is a no-op. Attaching the constant to b first, a + (b + k), defeats the sharing: 2268 / 1024 / 1300, 17–22% smaller under the two optimising scripts and 9% larger under yosys_default. One design, one tool version (0.33), generic gates. Stylised.

A follow-up to chip-abc-sweep and chip-ppa-loop: the earlier proposer files and a 16-adder and 8-multiplier sweep are scored under five ABC scripts, and every mapped netlist is proved equivalent to its reference (none failed). For the adder the best rewrite is 0.80–0.86× the reference under the same script, but the reference under its best script is already 0.61× its default score, so much of the headline gain was the script. For the multiplier no rewrite beats a * b under any script; the only gain (0.90×) is from the script. Stylised: two designs, one Yosys version, a session-written proposer, generic-gate counts rather than layout.

A follow-up to chip-ppa-loop on three small blocks where written structure matters. Every candidate is proved equivalent to its reference by a Yosys miter before its generic-gate cells×depth counts. Popcount: no real gain (0.98×). Absolute difference: 0.86×, a structure the sweep also contains. Leading-zero count: the session-written rewrites reach 0.80× but a no-model sweep reaches 0.56× (depth 8 against 11) and beats the proposer in 168 of 200 equal-budget draws. Also fixes a gate bug that rejected correct ROM-style tables. Fifteen attempts by one author, one tool version, gate counts only.

A follow-up to chip-ppa-logic: its 34 equivalent candidates for popcount, leading-zero count (clz16) and absolute difference are re-scored under five ABC scripts, and every mapped netlist is proved equivalent to the reference (none of 170 failed). On clz16 the verdict flips with the script: the no-model sweep wins under the default and dc2 scripts (344, 405), while a session-written nibble-combine file wins under three others (216–336 against the sweep’s 344–462); the overall best is 0.35× the reference’s default score. Popcount’s winner holds under all five scripts; absolute difference’s under three. Stylised: three tiny blocks, one Yosys version, hand-written proposer files, generic-gate cells×depth rather than layout.

A follow-up to chip-ppa-script on a 4×4 unsigned multiply-accumulate (a×b + c): three hand-written proposer files and a 12-config sweep (chain, tree or carry-save summation, c first or last) are scored under five ABC scripts, and every mapped netlist is proved equivalent to the reference (none failed; one seeded fault is rejected by the gate). Under the default script nothing beats the reference (1.06× its cells×depth), and under three of five scripts the best rewrite is 1.04–1.10×. Only carry-save forms win, under dch (0.91×) and a resyn2-style script (0.94×); the overall best is 0.93× the reference under its own best script. Stylised: one tiny design, one Yosys version, a generic-gate library, proposer files written by the session agent.

A follow-up to chip-ppa-mac: the same 17 candidates for a 4×4 unsigned multiply-accumulate are mapped to SkyWater SKY130 HD cells with ABC under four scripts, and every mapped netlist is proved equal to the reference (none failed). Carry-save forms are 3–17% better in area×delay under three scripts and 6–11% worse under a resyn2-style script; the plain a*b+c under that script is the best design overall. The generic cells×depth score agrees only weakly with cell-level area×delay (Spearman 0.20 over 64 pairs; 0.74 for cells against area, 0.26 for depth against delay). Stylised: one tiny design, one tool version and corner, ABC's load-free delay estimate, no place and route, session-written proposer files rather than an API model.

A follow-up to chip-ppa-sky130mac: every one of 800 (design, ABC pass sequence of length ≤3) points is evaluated, so the optimum is known: 1062 µm²·ns for the carry-save MAC, 11% below the best earlier script, and its netlist is proved equal to the reference. The landscape is needle-like (0.1% of points within 1% of the optimum; 108 sequences make ABC abort). At equal budgets of 10, 20 and 40 evaluations over 200 seeds, random search and hill climbing reach a median 1.135, 1.117/1.095 and 1.095/1.088 times the optimum, differences within noise at two of three budgets. One attempt of 40 session-written proposals reaches 1.088. Stylised: one 4×4 design pair, ABC's static delay estimate, no placement, not a language-model benchmark.

A generator for an 8-8-4 integer MLP engine with P multiply-accumulate lanes and 4-, 6- or 8-bit weights, simulated in Icarus Verilog and matched bit for bit and cycle for cycle against an integer NumPy reference in all 12 configurations. Synthesised with Yosys to generic gates, latency falls from 110 to 20 cycles as lanes go from 1 to 8 while area grows about 3× to 4×, so cells×cycles is smallest at 4 lanes for every width. 6 bits matched float accuracy on the toy task; 4 bits lost about 3 points. Stylised: one synthetic task and seed, weights baked into logic, gate counts rather than layout, nothing about a real chip.

Thirteen small designs (adders, multipliers, FIFOs) pushed through generic gate counting, Yosys/ABC mapping onto the SKY130 HD library, and an OpenROAD flow with placement, clock tree, global routing and timing repair. Generic gate count stays within 5.1–5.8 um² per gate for combinational logic but is about 3× higher per gate for FIFOs, whose flops dominate; mapping makes a ripple and a + adder identical. Layout adds 0–28% area (most where timing needs repair), and wires add 3–19% to delay before repair. The ABC clock target did not change the netlist at all. Stylised: tiny designs, one corner, global-route parasitics only, no detailed route or DRC, nothing about a fabricated chip.

An R×C systolic-array generator for the 8-8-4 integer MLP, simulated in Icarus Verilog and matched bit for bit and cycle for cycle against an integer NumPy reference in all 12 configurations (batch of 4). Against the MAC-lane engine of chip-accel at 4, 6 and 8 bits, synthesised with the same Yosys generic-gate script, the array has 1.6× to 1.8× more cells×cycles at its best shape (a negative result), but lower latency: 40 cycles for 4×8 against 80 for 8 MAC lanes, at about 3.9× the cells at 4 bits. Stylised: fan-in 8, one network, gate counts rather than area, no clock, power or layout.

A batch-size sweep (R = 4, 8, 16, 4-bit weights) of the output-stationary systolic generator from chip-systolic, simulated in Icarus Verilog and matched to an integer NumPy reference and the cycle formula in all 6 configurations, then scored with Yosys against the MAC-lane engine of chip-accel. A negative result: the best array has 1.6×, 2.1× and 2.9× the cells×cycles of 4 MAC lanes at R = 4, 8 and 16, because array area grows with the batch while MAC-lane area does not, even though it needs far fewer cycles (83 against 464 at R = 16). Stylised: fan-in 8, one network, an array that grows a row per vector, gate counts rather than area, no clock, power or layout.

Output-stationary arrays with R = 1, 2 and 4 rows, each reused for 32 vectors, simulated in Icarus Verilog and matched to an integer NumPy reference and the cycle formula in all 6 configurations, then scored with Yosys against the MAC-lane engine of chip-accel. A negative result: the best array (1×4) has 1.35× the cells×cycles per vector of 4 MAC lanes (65702 against 48546), and per-vector cost rises with the number of rows. Stylised: fan-in 8, one network, gate counts rather than area, no clock, power or layout.

The small output-stationary arrays of chip-systolic-small on an F-F-4 quantised MLP with F = 8, 16 and 32 (4-bit weights), all 12 array configurations matched to an integer NumPy reference and the cycle formula in Icarus Verilog, scored with Yosys against MAC-lane engines. A negative result: the best array costs 1.36×, 1.25× and 1.26× the cells×cycles per vector of the best MAC engine at F = 8, 16 and 32, so the gap narrows but does not close. Stylised: one seed, gate counts rather than area, no clock, power or layout, and some optima at the edge of the sweep.

The F-F-4 quantised-MLP comparison of chip-systolic-fanin with wider grids (C up to 16, P up to 32, F = 16 and 32), all 12 array configurations matched to an integer NumPy reference in Icarus Verilog and scored with Yosys. A negative result: the earlier optima were at the sweep edge and move inward (best array 2×8, best MAC engine P = 16 at F = 32), but the best array still costs 1.25× (F = 16) and 1.20× (F = 32) the cells×cycles per vector of the best MAC engine. Stylised: one network family, one seed, generic-gate counts, no layout.

The quantised-MLP comparison of chip-systolic-fanin on an F-8-4 network (F = 8, 16, 32; 4-bit weights), all 12 array configurations matched to an integer NumPy reference in Icarus Verilog and scored with Yosys against MAC-lane engines. A negative result: the best MAC engine wins at every F, by 1.35×, 1.22× and 1.20× in cells×cycles per vector, so the gap narrows but does not close. One network family, one seed, gate counts only; no layout or power.

Every MAC-lane count P = 1–20 of chip-accel's engine on an F-16-4 quantised network (F = 16, 32), all 40 designs simulated in Icarus Verilog bit for bit against an integer NumPy reference with measured cycles equal to the formula, then scored with Yosys. The best P is 8 at F = 16 and 16 at F = 32, so the earlier hand-picked sweep already contained the optimum; P > 16 only adds cells at equal cycles, and no non-power-of-two P wins (best is 44–62% behind). Cell count is far from monotone in P (F = 32: P = 15 has 2.4× the cells of P = 16), a possible generator artefact left untested. One network family, one seed, gate counts only; no layout or power.

The chip-systolic-hidden comparison repeated on an F-16-4 quantised network (F = 16, 32; 4-bit weights), all 8 array configurations matched to an integer NumPy reference in Icarus Verilog and scored with Yosys against MAC-lane engines up to P = 16. A negative result: the best MAC engine wins at both F, by 1.30× and 1.27× in cells×cycles per vector. At F = 32 the best lane count (P = 16, 3% ahead of P = 8) is again the largest tried, so its optimum may lie further out. One network family, one seed, gate counts only; no layout or power.

The chip-systolic-hidewide comparison (F-16-4 quantised network, F = 16, 32) extended to MAC engines with P up to 32 lanes and arrays up to 4×8 and 2×16, every design simulated in Icarus Verilog against an integer NumPy reference and scored with Yosys. A negative result: the best MAC engine still wins, by 1.30× and 1.28× in cells×cycles per vector. P = 32 adds no cycles over P = 16 (only 16 hidden outputs) and a 0.7% cell-count difference at F = 32; 4×8 does not beat 2×8. One network family, one seed, gate counts only; no layout or power.

The 20 designs of chip-systolic-p32 (six output-stationary arrays and four MAC-lane engines on an F-16-4 quantised network, F = 16, 32), each simulated against an integer NumPy reference and then scored with Yosys under five ABC scripts. A negative result for arrays: the best MAC engine wins in all ten F × script cases, by 1.28× to 1.60× in cells × cycles per vector, so the size of the lead depends on the script but the ranking does not. Stylised: one network, one seed, generic-gate counts, no layout.

chip-systolic-p32 found the 32-lane MAC engine smaller than the 16-lane one although both take the same cycles. Re-synthesised with three model seeds and three Yosys/abc flows at F = 16 and 32, the sign depends on the flow: P = 32 is smaller in all 6 cases under two flows and larger in all 6 under a four-gate library, by 47 to 699 cells (1–10%). That swing is far above the 0.7% margin used to rank the best design earlier, so that ranking should be discarded. Three seeds, one tool version, generic-gate counts only; the mechanism is not traced.

Follow-up to chip-macp32cells. Counting cells of the 16- and 32-lane MAC engines (identical cycles, F = 16, three seeds) after the word-level, bit-level and abc stages of one Yosys script: the 32-lane engine is 640–770 cells larger at the word level but about 500 cells smaller after techmap, and abc only trims the gap to 270–410. The sign is therefore set before abc runs. Which pass removes the extra lanes was not identified. Preliminary; one Yosys version, generic-gate counts.

Follow-up to chip-p32netlist. Running the fine passes of Yosys 0.33 one at a time on the 16- and 32-lane MAC engines (identical cycles, F = 16, three seeds): the 32-lane engine is still about 2,100 cells larger after techmap and 114–125 cells smaller after the next opt -fast, before any abc; abc -fast adds about 400 more. It also corrects the earlier project: Yosys 0.33’s -run :abc runs abc -fast, so its “pre-abc” column was post-abc. Localised to a pass, not explained; one Yosys version, generic cell counts. Stylised.

A 64-16-10 ReLU MLP trained on the real scikit-learn digits images (1797 8×8 scans, 70/30 splits, 5 seeds; float test accuracy 96.8%), quantised after training to W-bit signed weights and A-bit unsigned activations (W, A = 2–8, 49 configurations). One multiply-accumulate lane is written in Verilog, simulated in Icarus Verilog and matched to NumPy on 64 real layer-1 dot products per configuration (all 49 agree), and scored with Yosys and ABC in generic gates. Accuracy holds to 96.3% at W5A5 (268 cells, −0.5 points), 94.8% at W4A4 (189 cells, −2.0 points) and collapses at 3 bits or fewer (7978–82% at W3, 31–34% at W2ndash;82% at W3 with 3-bit or wider activations, 3178–82% at W3, 31–34% at W2ndash;34% at W2) or at 2-bit activations; widening beyond 6 bits buys nothing. Lane cells are not monotonic in width (ABC noise). Limitations: one small network and dataset, symmetric max-scaled quantisation with no quantisation-aware training (so the 2–3 bit collapse is a property of that scheme), generic-gate counts not square microns, one lane rather than a full accelerator, no clock, power or layout.

Follow-up to chip-digits-qat, whose per-channel quantiser rescaled each accumulator in float and so was not a hardware lane. Here each output channel gets a scale 2^e; the rescale becomes a left shift of the layer-1 accumulator to a common unit followed by one common right shift, and a left shift of each layer-2 logit. The forward pass is pure integer and a test compares it with a float64 recomputation (exact for powers of two). Two exponent rules are compared with chip-digits max scaling, chip-digits-qat MSE clipping and the float per-channel reference on the same 64-16-10 MLP and five scikit-learn digits splits: smallest non-clipping exponent (pot_max), and the exponent within three of that minimising each column's squared weight error (pot_mse). At W2A4, pot_mse reaches 70.5% (baseline 33.9%, per-tensor clip 61.9%); at W3A4 87.9% (clip 90.8%, float-scale per-channel 91.5%, so rounding scales to powers of two costs about 3.5 points there); at W4A4 94.4% (float 96.8%). The shifts are small: at most 4 distinct net shifts in layer 1 and 2 in layer 2 over the five splits, i.e. two and one mux2 stages per channel. Limitations: one small network and dataset, five splits with spreads of several points at W≤3, no QAT, gate cost counted as shifter stages only and not synthesised, exponent search window of four values. All inputs are measured on the dataset; none is assumed.

Follow-up to chip-digits, whose max-scaled post-training quantisation collapsed at 3-bit weights (81% at W3A4 against 96.8% float). On the same 64-16-10 MLP and five scikit-learn digits splits, four quantisers are compared for W = 2–4, A = 3–5: the baseline max scale; a per-tensor scale chosen to minimise weight MSE (clipping); per-output-channel max scales; and quantisation-aware training (300 full-batch epochs, straight-through estimator). The two per-tensor methods are integer-exact in the same lane specification, so the lane gate counts of chip-digits apply unchanged. At W3A4 the accuracy is 80.7% (baseline), 90.8% (clip), 91.5% (per-channel, float rescale, not an integer lane) and 90.9% (QAT); at W4A4 94.8%, 94.4%, 95.7% and 95.7%; at W2 only clipping gets above 60% and QAT fine-tuning is worse than the baseline at A=3 (28.5% against 32.8%). Limitations: one small network and dataset, five splits (minimum accuracies are in results.txt, spreads of several points at W≤3), QAT hyperparameters untuned, per-channel rescale hardware not built or costed, generic gates not area. All inputs are measured on the dataset; none is assumed.