What does a no-model baseline repair when a scripted RTL checker is the only feedback?

What it found

A companion to chip-rtl-loop: a four-stage checker (compile, lint, simulation, SAT miter) over ten small Verilog tasks, with a random-mutation hill-climbing baseline that uses no model. Given 1, 2 or 3 injected faults and 60 checker evaluations, the baseline repairs 9/20, 4/20 and 4/20 cases. The session agent (Claude) passed all ten tasks on its first attempt, so the feedback rounds were never exercised and no pass-rate-versus-rounds curve is reported. Preliminary: tiny tasks, one attempt, mutation faults unlike a language model's mistakes, and the optional API proposer is untested.

Paper, code and results

• README and method
• Experiments and results
• Code
• Tests

More in LLM chip design loops

• Does a rewrite proposer beat a parameter sweep on area and depth when every rewrite must be proved equivalent?Equivalence-gated area/depth rewrites of a 16-bit adder and 6x6 multiplier against a no-model parameter sweep; best adder 0.85x the reference cells×depth, tied by the sweep, no multiplier gain (stylised, gate counts).
• How does generic-gate area grow with bit width for adders, shifters, popcount and multipliers?How generic-gate cells and depth scale with bit width for seven arithmetic blocks: adder, comparator and mux are near-linear, the multiplier quadratic (exponent 2.19), and adder depth grows ~2×W (stylised, generic gates).
• Does writing a fixed-weight multiplier as shift-and-add with canonical signed digits beat Yosys's x * K?Fixed-weight multipliers for all 255 8-bit constants: Yosys's x * K tracks binary shift-add (Pearson 0.97 with set bits), and a canonical-signed-digit form has 33% fewer generic-gate cells at similar depth (every form proved equivalent).
• Does sharing sub-sums across a bank of fixed-weight multipliers cut gates beyond per-constant shift-and-add?A bank of fixed-weight multipliers sharing sub-sums (multiple-constant multiplication): 9% fewer generic-gate cells than per-constant signed-digit shift-add at 2 constants and about 20% fewer at 8 and 16 (43% fewer than Yosys's *), every form proved equivalent; random constants, not trained weights.
• How many gates could an exact 4-input rewriter still remove from Yosys/ABC netlists?How many gates an exact 4-input rewriter could still remove from real Yosys/ABC netlists: none in 28 of 30 runs (1 gate in two), even where the default script beats plain mapping by 25 to 42%, so the flow's gains are not local.
• How many gates above the proven minimum does Yosys/ABC use for 4-input logic?How far above the SAT-proven minimum gate count Yosys/ABC lands on 4-input logic: the default flow is exactly optimal on only 34% of sampled functions (mean 1.19 gates above, max 4), and a heavier script is worse.

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Other research topics

Proper scoring & elicitation28Effort & peer prediction9Verification games & slashing19Detection & tolerances14Markets as routers13Prediction-market design9Paying contributors8Decentralised training systems23Digital twins & sim-to-real164LLM chip design loops40Robot manufacturing loops53Ambient AI assistant46Self-replicating manufacturing34Simulation-first design64Engineered clothing45Task-specific AI accelerators40Algorithmic chip-design loops42Open-source purpose-built robots44The software-engineering loop43Adversarial human imitation41Open-source residential construction41Autonomous multi-angle capture34Sensing, imaging and 3D31Energy supply and dense energy storage39Robot societies among people31Agentic co-design of low-cost robots27Laundry-hanging robots25Machine learning on qualitative data23Robots on the building site27Civilizations & group psychology1History & human sciences1

Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.