How does generic-gate area grow with bit width for adders, shifters, popcount and multipliers?

What it found

Seven behavioural blocks synthesised by Yosys 0.33 to generic gates at widths 4–64. Cell counts for the adder, comparator, equality and 4:1 mux are close to linear in width (fitted exponent 1.00–1.13); the multiplier is quadratic (2.19 overall, 2.06 on the largest widths); the barrel shifter sits at 1.27–1.35. Logic depth scales differently from cells: the default-script adder's depth grows about 2×W (7 to 125) while the comparator's grows slowly (5 to 16). Preliminary: five widths, one tool version, generic gates rather than library area, no confidence intervals.

A figure from its own output

Paper, code and results

• README and method
• Experiments and results
• Code
• Tests

More in LLM chip design loops

• Does writing a fixed-weight multiplier as shift-and-add with canonical signed digits beat Yosys's x * K?Fixed-weight multipliers for all 255 8-bit constants: Yosys's x * K tracks binary shift-add (Pearson 0.97 with set bits), and a canonical-signed-digit form has 33% fewer generic-gate cells at similar depth (every form proved equivalent).
• Does sharing sub-sums across a bank of fixed-weight multipliers cut gates beyond per-constant shift-and-add?A bank of fixed-weight multipliers sharing sub-sums (multiple-constant multiplication): 9% fewer generic-gate cells than per-constant signed-digit shift-add at 2 constants and about 20% fewer at 8 and 16 (43% fewer than Yosys's *), every form proved equivalent; random constants, not trained weights.
• How many gates could an exact 4-input rewriter still remove from Yosys/ABC netlists?How many gates an exact 4-input rewriter could still remove from real Yosys/ABC netlists: none in 28 of 30 runs (1 gate in two), even where the default script beats plain mapping by 25 to 42%, so the flow's gains are not local.
• How many gates above the proven minimum does Yosys/ABC use for 4-input logic?How far above the SAT-proven minimum gate count Yosys/ABC lands on 4-input logic: the default flow is exactly optimal on only 34% of sampled functions (mean 1.19 gates above, max 4), and a heavier script is worse.
• Does the ABC synthesis script matter as much as the written RTL structure for adder and multiplier area and depth?Sweeps five ABC scripts over five adder and eight multiplier structures (all proved equivalent): the script moves cells×depth by up to 1.75× for one adder, while all eight multiplier structures score identically (stylised, generic-gate).
• Does the order or naming of equivalent Verilog change what Yosys and ABC synthesise?Whether equivalent Verilog that differs only in wire names, statement order or the order of added operands synthesises to the same size: names and statement order never change cells×depth, operand order does for one carry-select adder (up to 1.43×, a 17% better result than the earlier sweep's best; stylised).

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.