Does the order or naming of equivalent Verilog change what Yosys and ABC synthesise?

research/chip-abc-order

Whether equivalent Verilog that differs only in wire names, statement order or the order of added operands synthesises to the same size: names and statement order never change cells×depth, operand order does for one carry-select adder (up to 1.43×, a 17% better result than the earlier sweep's best; stylised).

4 tests

What it found

Provably equivalent rewrites of generated adder and multiplier RTL (random wire names, shuffled statements, shuffled order of added operands; 864 scored variants, every text proved equivalent to its reference) are scored under three ABC scripts. Names and statement order never change cells×depth. Operand order changes one carry-select adder by up to 1.43× within a script, and its best variant under dch is 17% better than the best adder chip-abc-sweep reported, so that earlier best was one draw from a distribution the text controls. Five other structures are unaffected. Stylised: two designs, one Yosys version, 12 seeds, generic-gate counts, cause not yet traced.

A figure from its own output

Figure produced by research/chip-abc-order: csel4_order — chip-abc-order/experiments/csel4_order.svg, written by the project's own experiment code.

Paper, code and results

More in LLM chip design loops

Do the blocks of a carry-select adder share a + b independently when every chain gets its own operand order?Tests whether carry-select blocks share a+b independently under mixed per-chain operand orders: the set of sharing blocks predicts Yosys's adder count in 400 of 400 random variants and fixes the cells x depth score (8 sets, one score each per ABC script); the cost is not additive across blocks (stylised, Yosys 0.33).
Which Yosys pass makes the operand order of a + b + constant change the synthesised adder?Finds the Yosys pass behind chip-abc-order's operand-order effect: opt_merge shares a+b between the two carry-select sums only when both are written with a and b first (4 of 36 operand orders); removing it widens the spread (up to 3.2×), so it was hiding variation. One adder, stylised.
Does letting Yosys share a common a + b make adders smaller under every ABC script?Tests whether letting Yosys share a common a + b shrinks adders: fewer cells in 54 of 55 design/script pairs but often deeper; stylised, Yosys 0.33.
Does writing the shared a + b sum of a carry-select adder explicitly change what Yosys and ABC synthesise?Writing the shared a + b sum of a carry-select adder by hand (explicitly, or as an incrementer) gives the same netlist Yosys already finds; attaching the constant to b first defeats the sharing and is 17-22% smaller under ABC's optimising scripts (stylised, Yosys 0.33).
Does a rewritten adder or multiplier still beat the reference once the ABC script is allowed to vary?Re-scores the chip-ppa-loop rewrites and sweep under five ABC scripts with every mapped netlist proved equivalent: the adder rewrite gain survives (0.80–0.86× the reference per script) but the multiplier's whole gain is the script (stylised, generic-gate).
Does an equivalence-gated rewrite loop beat a parameter sweep on popcount, leading-zero count and absolute difference?Equivalence-gated rewrites of 16-bit popcount, 16-bit leading-zero count and 8-bit |a−b| against a no-model sweep: popcount 0.98×, |a−b| 0.86×, but on leading-zero count the sweep (0.56×) beats the session-written rewrites (0.80×) in 168 of 200 equal-budget draws (stylised, gate counts).

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.