Does the ABC synthesis script matter as much as the written RTL structure for adder and multiplier area and depth?
research/chip-abc-sweep
Sweeps five ABC scripts over five adder and eight multiplier structures (all proved equivalent): the script moves cells×depth by up to 1.75× for one adder, while all eight multiplier structures score identically (stylised, generic-gate).
What it found
A follow-up to chip-ppa-loop: five ABC scripts are applied to five written 16-bit adder structures and eight 6×6 multiplier structures, each proved equivalent to its reference by a Yosys miter. For the adder, cells×depth moves by up to 1.75× with the script for one structure and 1.18–1.94× across structures for a fixed script; the best pair is 0.48× the default-script plain adder. All eight multiplier structures score identically under each script, yet the script alone moves them by 1.17×. Stylised: two designs, one Yosys version, generic-gate counts rather than layout.
A figure from its own output
Paper, code and results
More in LLM chip design loops
- Does the order or naming of equivalent Verilog change what Yosys and ABC synthesise?Whether equivalent Verilog that differs only in wire names, statement order or the order of added operands synthesises to the same size: names and statement order never change cells×depth, operand order does for one carry-select adder (up to 1.43×, a 17% better result than the earlier sweep's best; stylised).
- Do the blocks of a carry-select adder share a + b independently when every chain gets its own operand order?Tests whether carry-select blocks share
a+bindependently under mixed per-chain operand orders: the set of sharing blocks predicts Yosys's adder count in 400 of 400 random variants and fixes the cells x depth score (8 sets, one score each per ABC script); the cost is not additive across blocks (stylised, Yosys 0.33). - Which Yosys pass makes the operand order of a + b + constant change the synthesised adder?Finds the Yosys pass behind
chip-abc-order's operand-order effect:opt_mergesharesa+bbetween the two carry-select sums only when both are written withaandbfirst (4 of 36 operand orders); removing it widens the spread (up to 3.2×), so it was hiding variation. One adder, stylised. - Does letting Yosys share a common a + b make adders smaller under every ABC script?Tests whether letting Yosys share a common
a + bshrinks adders: fewer cells in 54 of 55 design/script pairs but often deeper; stylised, Yosys 0.33. - Does writing the shared a + b sum of a carry-select adder explicitly change what Yosys and ABC synthesise?Writing the shared
a + bsum of a carry-select adder by hand (explicitly, or as an incrementer) gives the same netlist Yosys already finds; attaching the constant tobfirst defeats the sharing and is 17-22% smaller under ABC's optimising scripts (stylised, Yosys 0.33). - Does a rewritten adder or multiplier still beat the reference once the ABC script is allowed to vary?Re-scores the
chip-ppa-looprewrites and sweep under five ABC scripts with every mapped netlist proved equivalent: the adder rewrite gain survives (0.80–0.86× the reference per script) but the multiplier's whole gain is the script (stylised, generic-gate).
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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.