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LLM chip design loops

Does writing the shared a + b sum of a carry-select adder explicitly change what Yosys and ABC synthesise?

research/chip-cse-style

Writing the shared a + b sum of a carry-select adder by hand (explicitly, or as an incrementer) gives the same netlist Yosys already finds; attaching the constant to b first defeats the sharing and is 17-22% smaller under ABC's optimising scripts (stylised, Yosys 0.33).

3 tests

What it found

Six equivalent 16-bit adder styles (each proved against a + b with a Yosys miter) are scored with three ABC scripts. Writing the shared sum by hand (p = a + b, y = p + 1) or as an incrementer (y = x + 1) gives exactly the netlist opt_merge finds for the plain a + b + 0 / a + b + 1 text (cells×depth 2090 / 1232 / 1665), so a hand common-subexpression rewrite is a no-op. Attaching the constant to b first, a + (b + k), defeats the sharing: 2268 / 1024 / 1300, 17–22% smaller under the two optimising scripts and 9% larger under yosys_default. One design, one tool version (0.33), generic gates. Stylised.

Paper, code and results

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.