Does fusing the accumulate into the partial-product tree beat multiply-then-add once the ABC script varies?
research/chip-ppa-mac
A fused 4×4 multiply-accumulate: no written rewrite beats a*b+c under the default or three of five ABC scripts, but carry-save forms win by up to 9% cells×depth under dch and resyn2 (stylised, generic-gate).
What it found
A follow-up to chip-ppa-script on a 4×4 unsigned multiply-accumulate (a×b + c): three hand-written proposer files and a 12-config sweep (chain, tree or carry-save summation, c first or last) are scored under five ABC scripts, and every mapped netlist is proved equivalent to the reference (none failed; one seeded fault is rejected by the gate). Under the default script nothing beats the reference (1.06× its cells×depth), and under three of five scripts the best rewrite is 1.04–1.10×. Only carry-save forms win, under dch (0.91×) and a resyn2-style script (0.94×); the overall best is 0.93× the reference under its own best script. Stylised: one tiny design, one Yosys version, a generic-gate library, proposer files written by the session agent.
A figure from its own output
Paper, code and results
More in LLM chip design loops
- Do the carry-save multiply-accumulate rewrites still win once mapped to real SKY130 cells, and does the generic-gate score predict that?The
chip-ppa-maccarry-save MAC rewrites mapped to SKY130 HD cells: the plaina*b+cunder its best script is the overall best, the generic-gate score ranks candidates only weakly like cell areaxdelay (Spearman 0.20; stylised, ABC delay estimate). - How rugged is the landscape of SKY130 area×delay over ABC pass sequences for a multiply-accumulate, and do simple searches beat random at 10–40 evaluations?An exhaustive 800-point table of SKY130 areaxdelay over ABC pass sequences for the MAC (optimum 11% below the best earlier script; needle-like landscape), with random search, hill climbing and session-written proposals compared at equal budget (stylised, preliminary).
- How do MAC-lane count and bit width trade area against latency in a tiny quantised-MLP accelerator?Parameterised MAC-lane accelerator for an 8-8-4 quantised MLP, bit- and cycle-exact against NumPy in Icarus; lanes x bit-width sweep puts the cells-times-cycles minimum at 4 lanes (stylised, generic-gate counts).
- How far do synthesis-only area and delay sit from placed-and-routed numbers on SKY130?Synthesis-only area and delay versus placed-and-routed OpenROAD numbers on SKY130 for 13 small designs (stylised, global-route estimates).
- Does an output-stationary systolic array beat a MAC-lane engine for a tiny quantised MLP?R x C output-stationary systolic MLP engine, bit- and cycle-exact against NumPy; at matched MACs it loses to
chip-accel's MAC lanes on cells-times-cycles (about 1.6x to 1.8x) but wins on latency (negative, stylised, generic-gate counts). - Does a larger batch let a systolic array catch a MAC-lane engine on a tiny quantised MLP?Batch-size sweep of the systolic MLP engine (R = 4, 8, 16): the array's cells-times-cycles disadvantage against
chip-accel's MAC lanes widens from 1.6x to 2.9x because its area grows with the batch (negative, stylised, generic-gate counts).
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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.