How do MAC-lane count and bit width trade area against latency in a tiny quantised-MLP accelerator?

What it found

A generator for an 8-8-4 integer MLP engine with P multiply-accumulate lanes and 4-, 6- or 8-bit weights, simulated in Icarus Verilog and matched bit for bit and cycle for cycle against an integer NumPy reference in all 12 configurations. Synthesised with Yosys to generic gates, latency falls from 110 to 20 cycles as lanes go from 1 to 8 while area grows about 3× to 4×, so cells×cycles is smallest at 4 lanes for every width. 6 bits matched float accuracy on the toy task; 4 bits lost about 3 points. Stylised: one synthetic task and seed, weights baked into logic, gate counts rather than layout, nothing about a real chip.

A figure from its own output

Paper, code and results

• README and method
• Experiments and results
• Code
• Tests

More in LLM chip design loops

• How far do synthesis-only area and delay sit from placed-and-routed numbers on SKY130?Synthesis-only area and delay versus placed-and-routed OpenROAD numbers on SKY130 for 13 small designs (stylised, global-route estimates).
• Does an output-stationary systolic array beat a MAC-lane engine for a tiny quantised MLP?R x C output-stationary systolic MLP engine, bit- and cycle-exact against NumPy; at matched MACs it loses to chip-accel's MAC lanes on cells-times-cycles (about 1.6x to 1.8x) but wins on latency (negative, stylised, generic-gate counts).
• Does a larger batch let a systolic array catch a MAC-lane engine on a tiny quantised MLP?Batch-size sweep of the systolic MLP engine (R = 4, 8, 16): the array's cells-times-cycles disadvantage against chip-accel's MAC lanes widens from 1.6x to 2.9x because its area grows with the batch (negative, stylised, generic-gate counts).
• Does a small systolic array reused over a stream of vectors beat a MAC-lane engine on a tiny quantised MLP?Small reused systolic arrays (R = 1, 2, 4 rows) against chip-accel's MAC lanes: even the best, 1x4, has 1.35x the cells-times-cycles per vector (65702 vs 48546) at fan-in 8 (negative, stylised, generic-gate counts).
• Does a wider fan-in let a small systolic array catch a MAC-lane engine on a tiny quantised MLP?Fan-in sweep (F = 8, 16, 32) of small systolic arrays against chip-accel's MAC lanes: the best array costs 1.36x, 1.25x and 1.26x the cells-times-cycles per vector of the best MAC engine, so the gap narrows but does not close (negative, stylised, generic-gate counts).
• Do the optima of the fan-in sweep move when columns and MAC lanes go past 8?Extends the fan-in sweep past its edges (C = 16, P = 32): the optima move inward and the best array still costs 1.25x (F = 16) and 1.20x (F = 32) the cells-times-cycles per vector of the best MAC engine (negative, stylised, generic-gate counts).

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.