How far do synthesis-only area and delay sit from placed-and-routed numbers on SKY130?

What it found

Thirteen small designs (adders, multipliers, FIFOs) pushed through generic gate counting, Yosys/ABC mapping onto the SKY130 HD library, and an OpenROAD flow with placement, clock tree, global routing and timing repair. Generic gate count stays within 5.1–5.8 um² per gate for combinational logic but is about 3× higher per gate for FIFOs, whose flops dominate; mapping makes a ripple and a + adder identical. Layout adds 0–28% area (most where timing needs repair), and wires add 3–19% to delay before repair. The ABC clock target did not change the netlist at all. Stylised: tiny designs, one corner, global-route parasitics only, no detailed route or DRC, nothing about a fabricated chip.

A figure from its own output

Paper, code and results

• README and method
• Experiments and results
• Code
• Tests

More in LLM chip design loops

• Does an output-stationary systolic array beat a MAC-lane engine for a tiny quantised MLP?R x C output-stationary systolic MLP engine, bit- and cycle-exact against NumPy; at matched MACs it loses to chip-accel's MAC lanes on cells-times-cycles (about 1.6x to 1.8x) but wins on latency (negative, stylised, generic-gate counts).
• Does a larger batch let a systolic array catch a MAC-lane engine on a tiny quantised MLP?Batch-size sweep of the systolic MLP engine (R = 4, 8, 16): the array's cells-times-cycles disadvantage against chip-accel's MAC lanes widens from 1.6x to 2.9x because its area grows with the batch (negative, stylised, generic-gate counts).
• Does a small systolic array reused over a stream of vectors beat a MAC-lane engine on a tiny quantised MLP?Small reused systolic arrays (R = 1, 2, 4 rows) against chip-accel's MAC lanes: even the best, 1x4, has 1.35x the cells-times-cycles per vector (65702 vs 48546) at fan-in 8 (negative, stylised, generic-gate counts).
• Does a wider fan-in let a small systolic array catch a MAC-lane engine on a tiny quantised MLP?Fan-in sweep (F = 8, 16, 32) of small systolic arrays against chip-accel's MAC lanes: the best array costs 1.36x, 1.25x and 1.26x the cells-times-cycles per vector of the best MAC engine, so the gap narrows but does not close (negative, stylised, generic-gate counts).
• Do the optima of the fan-in sweep move when columns and MAC lanes go past 8?Extends the fan-in sweep past its edges (C = 16, P = 32): the optima move inward and the best array still costs 1.25x (F = 16) and 1.20x (F = 32) the cells-times-cycles per vector of the best MAC engine (negative, stylised, generic-gate counts).
• Does the array/MAC-engine gap change when the hidden width is fixed at 8 and only the input fan-in grows?Fixes the hidden width at 8 and sweeps the input fan-in F = 8, 16, 32: the best MAC engine still beats the best systolic array, by 1.35x, 1.22x and 1.20x in cells-times-cycles per vector (negative, stylised, generic-gate counts).

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.