How rugged is the landscape of SKY130 area×delay over ABC pass sequences for a multiply-accumulate, and do simple searches beat random at 10–40 evaluations?
research/chip-scriptsearch
An exhaustive 800-point table of SKY130 areaxdelay over ABC pass sequences for the MAC (optimum 11% below the best earlier script; needle-like landscape), with random search, hill climbing and session-written proposals compared at equal budget (stylised, preliminary).
What it found
A follow-up to chip-ppa-sky130mac: every one of 800 (design, ABC pass sequence of length ≤3) points is evaluated, so the optimum is known: 1062 µm2·ns for the carry-save MAC, 11% below the best earlier script, and its netlist is proved equal to the reference. The landscape is needle-like (0.1% of points within 1% of the optimum; 108 sequences make ABC abort). At equal budgets of 10, 20 and 40 evaluations over 200 seeds, random search and hill climbing reach a median 1.135, 1.117/1.095 and 1.095/1.088 times the optimum, differences within noise at two of three budgets. One attempt of 40 session-written proposals reaches 1.088. Stylised: one 4×4 design pair, ABC's static delay estimate, no placement, not a language-model benchmark.
A figure from its own output
Paper, code and results
More in LLM chip design loops
- How do MAC-lane count and bit width trade area against latency in a tiny quantised-MLP accelerator?Parameterised MAC-lane accelerator for an 8-8-4 quantised MLP, bit- and cycle-exact against NumPy in Icarus; lanes x bit-width sweep puts the cells-times-cycles minimum at 4 lanes (stylised, generic-gate counts).
- How far do synthesis-only area and delay sit from placed-and-routed numbers on SKY130?Synthesis-only area and delay versus placed-and-routed OpenROAD numbers on SKY130 for 13 small designs (stylised, global-route estimates).
- Does an output-stationary systolic array beat a MAC-lane engine for a tiny quantised MLP?R x C output-stationary systolic MLP engine, bit- and cycle-exact against NumPy; at matched MACs it loses to
chip-accel's MAC lanes on cells-times-cycles (about 1.6x to 1.8x) but wins on latency (negative, stylised, generic-gate counts). - Does a larger batch let a systolic array catch a MAC-lane engine on a tiny quantised MLP?Batch-size sweep of the systolic MLP engine (R = 4, 8, 16): the array's cells-times-cycles disadvantage against
chip-accel's MAC lanes widens from 1.6x to 2.9x because its area grows with the batch (negative, stylised, generic-gate counts). - Does a small systolic array reused over a stream of vectors beat a MAC-lane engine on a tiny quantised MLP?Small reused systolic arrays (R = 1, 2, 4 rows) against
chip-accel's MAC lanes: even the best, 1x4, has 1.35x the cells-times-cycles per vector (65702 vs 48546) at fan-in 8 (negative, stylised, generic-gate counts). - Does a wider fan-in let a small systolic array catch a MAC-lane engine on a tiny quantised MLP?Fan-in sweep (F = 8, 16, 32) of small systolic arrays against
chip-accel's MAC lanes: the best array costs 1.36x, 1.25x and 1.26x the cells-times-cycles per vector of the best MAC engine, so the gap narrows but does not close (negative, stylised, generic-gate counts).
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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.