Do the carry-save multiply-accumulate rewrites still win once mapped to real SKY130 cells, and does the generic-gate score predict that?

What it found

A follow-up to chip-ppa-mac: the same 17 candidates for a 4×4 unsigned multiply-accumulate are mapped to SkyWater SKY130 HD cells with ABC under four scripts, and every mapped netlist is proved equal to the reference (none failed). Carry-save forms are 3–17% better in area×delay under three scripts and 6–11% worse under a resyn2-style script; the plain a*b+c under that script is the best design overall. The generic cells×depth score agrees only weakly with cell-level area×delay (Spearman 0.20 over 64 pairs; 0.74 for cells against area, 0.26 for depth against delay). Stylised: one tiny design, one tool version and corner, ABC's load-free delay estimate, no place and route, session-written proposer files rather than an API model.

A figure from its own output

Paper, code and results

• README and method
• Experiments and results
• Code
• Tests

More in LLM chip design loops

• How rugged is the landscape of SKY130 area×delay over ABC pass sequences for a multiply-accumulate, and do simple searches beat random at 10–40 evaluations?An exhaustive 800-point table of SKY130 areaxdelay over ABC pass sequences for the MAC (optimum 11% below the best earlier script; needle-like landscape), with random search, hill climbing and session-written proposals compared at equal budget (stylised, preliminary).
• How do MAC-lane count and bit width trade area against latency in a tiny quantised-MLP accelerator?Parameterised MAC-lane accelerator for an 8-8-4 quantised MLP, bit- and cycle-exact against NumPy in Icarus; lanes x bit-width sweep puts the cells-times-cycles minimum at 4 lanes (stylised, generic-gate counts).
• How far do synthesis-only area and delay sit from placed-and-routed numbers on SKY130?Synthesis-only area and delay versus placed-and-routed OpenROAD numbers on SKY130 for 13 small designs (stylised, global-route estimates).
• Does an output-stationary systolic array beat a MAC-lane engine for a tiny quantised MLP?R x C output-stationary systolic MLP engine, bit- and cycle-exact against NumPy; at matched MACs it loses to chip-accel's MAC lanes on cells-times-cycles (about 1.6x to 1.8x) but wins on latency (negative, stylised, generic-gate counts).
• Does a larger batch let a systolic array catch a MAC-lane engine on a tiny quantised MLP?Batch-size sweep of the systolic MLP engine (R = 4, 8, 16): the array's cells-times-cycles disadvantage against chip-accel's MAC lanes widens from 1.6x to 2.9x because its area grows with the batch (negative, stylised, generic-gate counts).
• Does a small systolic array reused over a stream of vectors beat a MAC-lane engine on a tiny quantised MLP?Small reused systolic arrays (R = 1, 2, 4 rows) against chip-accel's MAC lanes: even the best, 1x4, has 1.35x the cells-times-cycles per vector (65702 vs 48546) at fan-in 8 (negative, stylised, generic-gate counts).

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.