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LLM chip design loops

Does letting Yosys share a common a + b make adders smaller under every ABC script?

research/chip-sharesign

Tests whether letting Yosys share a common a + b shrinks adders: fewer cells in 54 of 55 design/script pairs but often deeper; stylised, Yosys 0.33.

3 tests

What it found

Eleven small adder-shaped designs whose outputs all contain a + b are written once so opt_merge shares the sum and once so it cannot (each pair proved equivalent). Scored under five ABC scripts, sharing gives fewer cells in 54 of 55 pairs (median ratio 0.76–0.85), but is deeper in 6–9 of 11 designs, so cells × depth favours it in 7–9 of 11. The sign flip seen on the 16-bit carry-select adder in chip-abc-orderpass does not appear. Stylised: generic gates, Yosys 0.33, no place and route.

A figure from its own output

Figure produced by research/chip-sharesign: sharesign
chip-sharesign/experiments/sharesign.svg, written by the project's own experiment code.

Paper, code and results

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.