How many gates could an exact 4-input rewriter still remove from Yosys/ABC netlists?

What it found

chip-exact4 found Yosys/ABC about 1.2 gates above the proven minimum on isolated 4-input functions. Here every gate of six small netlists (adder, multiplier, comparator, popcount, shifter, priority encoder) under five ABC flows is checked against that exact minimum over all its 4-leaf cuts, counting only logic a local replacement could delete. The disjoint headroom is 0 gates in 28 of 30 runs and 1 gate in the other two, even though the default script cuts 25–42% of the gates of plain mapping on add16 and prio16: the flow’s gains are not local, so an exact small-cone rewrite proposer would find almost nothing. Stylised: six blocks, gate count with free inverters, one Yosys build; replacement circuits were not constructed.

A figure from its own output

Paper, code and results

• README and method
• Experiments and results
• Code
• Tests

More in LLM chip design loops

• How many gates above the proven minimum does Yosys/ABC use for 4-input logic?How far above the SAT-proven minimum gate count Yosys/ABC lands on 4-input logic: the default flow is exactly optimal on only 34% of sampled functions (mean 1.19 gates above, max 4), and a heavier script is worse.
• Does the ABC synthesis script matter as much as the written RTL structure for adder and multiplier area and depth?Sweeps five ABC scripts over five adder and eight multiplier structures (all proved equivalent): the script moves cells×depth by up to 1.75× for one adder, while all eight multiplier structures score identically (stylised, generic-gate).
• Does the order or naming of equivalent Verilog change what Yosys and ABC synthesise?Whether equivalent Verilog that differs only in wire names, statement order or the order of added operands synthesises to the same size: names and statement order never change cells×depth, operand order does for one carry-select adder (up to 1.43×, a 17% better result than the earlier sweep's best; stylised).
• Do the blocks of a carry-select adder share a + b independently when every chain gets its own operand order?Tests whether carry-select blocks share a+b independently under mixed per-chain operand orders: the set of sharing blocks predicts Yosys's adder count in 400 of 400 random variants and fixes the cells x depth score (8 sets, one score each per ABC script); the cost is not additive across blocks (stylised, Yosys 0.33).
• Which Yosys pass makes the operand order of a + b + constant change the synthesised adder?Finds the Yosys pass behind chip-abc-order's operand-order effect: opt_merge shares a+b between the two carry-select sums only when both are written with a and b first (4 of 36 operand orders); removing it widens the spread (up to 3.2×), so it was hiding variation. One adder, stylised.
• Does letting Yosys share a common a + b make adders smaller under every ABC script?Tests whether letting Yosys share a common a + b shrinks adders: fewer cells in 54 of 55 design/script pairs but often deeper; stylised, Yosys 0.33.

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.