Does sharing sub-sums across a bank of fixed-weight multipliers cut gates beyond per-constant shift-and-add?

research/chip-mcm

A bank of fixed-weight multipliers sharing sub-sums (multiple-constant multiplication): 9% fewer generic-gate cells than per-constant signed-digit shift-add at 2 constants and about 20% fewer at 8 and 16 (43% fewer than Yosys's *), every form proved equivalent; random constants, not trained weights.

6 tests

What it found

A follow-up to chip-constmul: one 8-bit input feeds a bank of M random 8-bit constants (M = 2, 4, 8, 16; 40 banks each), written three ways — the * operator, per-constant canonical-signed-digit (CSD) shift-add, and a greedy shared-sub-sum (MCM) form — scored by Yosys 0.33 in generic gates, every variant proved equivalent to the operator form. Sharing uses 9% fewer cells than per-constant CSD at M = 2 and about 20% fewer at M = 8 and 16 (690 vs 866 at M = 16; 43% fewer than the operator), fewer in 130 of 160 banks and more in 2. Adders removed in the source predict cells saved (Pearson 0.875, about 15 cells per adder). Sharing also recovers the depth CSD loses on large banks (28.2 vs 33.2 at M = 16). Preliminary: random rather than trained weights, one greedy heuristic, one tool version, generic gates rather than library area.

A figure from its own output

Figure produced by research/chip-mcm: cells_by_bank — chip-mcm/experiments/cells_by_bank.svg, written by the project's own experiment code.

Paper, code and results

More in LLM chip design loops

How many gates could an exact 4-input rewriter still remove from Yosys/ABC netlists?How many gates an exact 4-input rewriter could still remove from real Yosys/ABC netlists: none in 28 of 30 runs (1 gate in two), even where the default script beats plain mapping by 25 to 42%, so the flow's gains are not local.
How many gates above the proven minimum does Yosys/ABC use for 4-input logic?How far above the SAT-proven minimum gate count Yosys/ABC lands on 4-input logic: the default flow is exactly optimal on only 34% of sampled functions (mean 1.19 gates above, max 4), and a heavier script is worse.
Does the ABC synthesis script matter as much as the written RTL structure for adder and multiplier area and depth?Sweeps five ABC scripts over five adder and eight multiplier structures (all proved equivalent): the script moves cells×depth by up to 1.75× for one adder, while all eight multiplier structures score identically (stylised, generic-gate).
Does the order or naming of equivalent Verilog change what Yosys and ABC synthesise?Whether equivalent Verilog that differs only in wire names, statement order or the order of added operands synthesises to the same size: names and statement order never change cells×depth, operand order does for one carry-select adder (up to 1.43×, a 17% better result than the earlier sweep's best; stylised).
Do the blocks of a carry-select adder share a + b independently when every chain gets its own operand order?Tests whether carry-select blocks share a+b independently under mixed per-chain operand orders: the set of sharing blocks predicts Yosys's adder count in 400 of 400 random variants and fixes the cells x depth score (8 sets, one score each per ABC script); the cost is not additive across blocks (stylised, Yosys 0.33).
Which Yosys pass makes the operand order of a + b + constant change the synthesised adder?Finds the Yosys pass behind chip-abc-order's operand-order effect: opt_merge shares a+b between the two carry-select sums only when both are written with a and b first (4 of 36 operand orders); removing it widens the spread (up to 3.2×), so it was hiding variation. One adder, stylised.

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.