Does the MAC engine beat a systolic array under every ABC script, not just Yosys's default?

What it found

The 20 designs of chip-systolic-p32 (six output-stationary arrays and four MAC-lane engines on an F-16-4 quantised network, F = 16, 32), each simulated against an integer NumPy reference and then scored with Yosys under five ABC scripts. A negative result for arrays: the best MAC engine wins in all ten F × script cases, by 1.28× to 1.60× in cells × cycles per vector, so the size of the lead depends on the script but the ranking does not. Stylised: one network, one seed, generic-gate counts, no layout.

A figure from its own output

Paper, code and results

• README and method
• Experiments and results
• Code
• Tests

More in LLM chip design loops

• Is P = 32 being smaller than P = 16 at equal cycles a real effect or a synthesis artefact?Re-synthesises the 16- and 32-lane MAC engines (same cycles) with three seeds and three Yosys flows: the sign of the cell-count gap depends on the flow, with swings of 1-10%, so chip-systolic-p32's 0.7% ranking is not reliable (artefact-sensitive, stylised, generic-gate counts).
• At which Yosys stage does the P = 32 versus P = 16 cell gap appear?Counts cells of the 16- and 32-lane MAC engines after the word-level, bit-level and abc stages: the 32-lane engine is bigger at the word level, about 500 cells smaller after techmap, so the chip-macp32cells gap is set before abc (localised, mechanism unexplained, stylised).
• Which Yosys pass flips the P = 32 versus P = 16 cell gap?Runs the Yosys fine passes one at a time on the 16- and 32-lane MAC engines: the P = 32 versus P = 16 sign flips (+2,100 to about -120 cells) at the first opt -fast after techmap, before any abc, and chip-p32netlist's pre-abc label is corrected (Yosys 0.33's -run :abc includes abc -fast). Stylised.
• How few bits can a MAC lane use to classify real handwritten digits before accuracy falls off a cliff?Weight and activation bit-width sweep of a 64-16-10 quantised MLP on the scikit-learn digits data (5 splits), with the MAC lane's gate count from Yosys and its RTL checked against NumPy: 4-bit weights and activations lose about 2 points of accuracy, 5 and 5 about 0.5, below 3 bits it collapses.
• Can per-channel power-of-two scales make the per-neuron quantiser an integer-exact MAC lane, and what accuracy does it keep at 2 to 4 weight bits?Giving each neuron of the digits MLP its own power-of-two weight scale turns the per-channel rescale into one or two shift stages and keeps the lane integer-exact: at W2A4 the MSE-chosen exponents reach 70.5% (against 62% for per-tensor clipping), but at W3A4 they give 87.9%, below clipping's 90.8%.
• Does clipping, per-channel scaling or quantisation-aware training move the 3-bit cliff of an MLP lane on real digits?MSE-optimal weight clipping lifts the 3-bit-weight digits MLP from 81% to 91% test accuracy at the same MAC-lane hardware and integer-exact; per-channel scales and QAT help at 4 bits (95.7% at W4A4, within 1.1 points of float) but QAT fails at 2 bits.

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.