At which Yosys stage does the P = 32 versus P = 16 cell gap appear?

research/chip-p32netlist

Counts cells of the 16- and 32-lane MAC engines after the word-level, bit-level and abc stages: the 32-lane engine is bigger at the word level, about 500 cells smaller after techmap, so the chip-macp32cells gap is set before abc (localised, mechanism unexplained, stylised).

3 tests

What it found

Follow-up to chip-macp32cells. Counting cells of the 16- and 32-lane MAC engines (identical cycles, F = 16, three seeds) after the word-level, bit-level and abc stages of one Yosys script: the 32-lane engine is 640–770 cells larger at the word level but about 500 cells smaller after techmap, and abc only trims the gap to 270–410. The sign is therefore set before abc runs. Which pass removes the extra lanes was not identified. Preliminary; one Yosys version, generic-gate counts.

Paper, code and results

More in LLM chip design loops

Which Yosys pass flips the P = 32 versus P = 16 cell gap?Runs the Yosys fine passes one at a time on the 16- and 32-lane MAC engines: the P = 32 versus P = 16 sign flips (+2,100 to about -120 cells) at the first opt -fast after techmap, before any abc, and chip-p32netlist's pre-abc label is corrected (Yosys 0.33's -run :abc includes abc -fast). Stylised.
How few bits can a MAC lane use to classify real handwritten digits before accuracy falls off a cliff?Weight and activation bit-width sweep of a 64-16-10 quantised MLP on the scikit-learn digits data (5 splits), with the MAC lane's gate count from Yosys and its RTL checked against NumPy: 4-bit weights and activations lose about 2 points of accuracy, 5 and 5 about 0.5, below 3 bits it collapses.
Can per-channel power-of-two scales make the per-neuron quantiser an integer-exact MAC lane, and what accuracy does it keep at 2 to 4 weight bits?Giving each neuron of the digits MLP its own power-of-two weight scale turns the per-channel rescale into one or two shift stages and keeps the lane integer-exact: at W2A4 the MSE-chosen exponents reach 70.5% (against 62% for per-tensor clipping), but at W3A4 they give 87.9%, below clipping's 90.8%.
Does clipping, per-channel scaling or quantisation-aware training move the 3-bit cliff of an MLP lane on real digits?MSE-optimal weight clipping lifts the 3-bit-weight digits MLP from 81% to 91% test accuracy at the same MAC-lane hardware and integer-exact; per-channel scales and QAT help at 4 bits (95.7% at W4A4, within 1.1 points of float) but QAT fails at 2 bits.
What does an all-open RTL flow report for small designs, and can it prove them equivalent?Reproducible open RTL flow (Yosys, Icarus, Verilator): gate count and depth for adders, a multiplier and a FIFO, SAT equivalence of two adders plus a broken-adder control. Gate counts, not silicon.
Which check catches an RTL bug: lint, random simulation or a formal equivalence proof?What lint, random simulation and a Yosys equivalence proof each catch, on 12 small RTL tasks (companion to chip-rtl-loop); mutation probe shows 30 of 389 rejected bugs are caught only by the formal proof. Session-written attempts, not an LLM benchmark.

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.