Does the MAC-engine lead survive MAC lanes up to P = 32 and arrays up to R = 4?

What it found

The chip-systolic-hidewide comparison (F-16-4 quantised network, F = 16, 32) extended to MAC engines with P up to 32 lanes and arrays up to 4×8 and 2×16, every design simulated in Icarus Verilog against an integer NumPy reference and scored with Yosys. A negative result: the best MAC engine still wins, by 1.30× and 1.28× in cells×cycles per vector. P = 32 adds no cycles over P = 16 (only 16 hidden outputs) and a 0.7% cell-count difference at F = 32; 4×8 does not beat 2×8. One network family, one seed, gate counts only; no layout or power.

A figure from its own output

Paper, code and results

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More in LLM chip design loops

• Does the MAC engine beat a systolic array under every ABC script, not just Yosys's default?Re-scores chip-systolic-p32's 20 designs under five ABC scripts: the best MAC engine beats the best systolic array in all ten F x script cases, by 1.28x to 1.60x (negative for arrays, stylised, generic-gate counts).
• Is P = 32 being smaller than P = 16 at equal cycles a real effect or a synthesis artefact?Re-synthesises the 16- and 32-lane MAC engines (same cycles) with three seeds and three Yosys flows: the sign of the cell-count gap depends on the flow, with swings of 1-10%, so chip-systolic-p32's 0.7% ranking is not reliable (artefact-sensitive, stylised, generic-gate counts).
• At which Yosys stage does the P = 32 versus P = 16 cell gap appear?Counts cells of the 16- and 32-lane MAC engines after the word-level, bit-level and abc stages: the 32-lane engine is bigger at the word level, about 500 cells smaller after techmap, so the chip-macp32cells gap is set before abc (localised, mechanism unexplained, stylised).
• Which Yosys pass flips the P = 32 versus P = 16 cell gap?Runs the Yosys fine passes one at a time on the 16- and 32-lane MAC engines: the P = 32 versus P = 16 sign flips (+2,100 to about -120 cells) at the first opt -fast after techmap, before any abc, and chip-p32netlist's pre-abc label is corrected (Yosys 0.33's -run :abc includes abc -fast). Stylised.
• How few bits can a MAC lane use to classify real handwritten digits before accuracy falls off a cliff?Weight and activation bit-width sweep of a 64-16-10 quantised MLP on the scikit-learn digits data (5 splits), with the MAC lane's gate count from Yosys and its RTL checked against NumPy: 4-bit weights and activations lose about 2 points of accuracy, 5 and 5 about 0.5, below 3 bits it collapses.
• Can per-channel power-of-two scales make the per-neuron quantiser an integer-exact MAC lane, and what accuracy does it keep at 2 to 4 weight bits?Giving each neuron of the digits MLP its own power-of-two weight scale turns the per-channel rescale into one or two shift stages and keeps the lane integer-exact: at W2A4 the MSE-chosen exponents reach 70.5% (against 62% for per-tensor clipping), but at W3A4 they give 87.9%, below clipping's 90.8%.

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.