Which MAC-lane count is best for a tiny quantised MLP if every P from 1 to 20 is built and checked?

What it found

Every MAC-lane count P = 1–20 of chip-accel's engine on an F-16-4 quantised network (F = 16, 32), all 40 designs simulated in Icarus Verilog bit for bit against an integer NumPy reference with measured cycles equal to the formula, then scored with Yosys. The best P is 8 at F = 16 and 16 at F = 32, so the earlier hand-picked sweep already contained the optimum; P > 16 only adds cells at equal cycles, and no non-power-of-two P wins (best is 44–62% behind). Cell count is far from monotone in P (F = 32: P = 15 has 2.4× the cells of P = 16), a possible generator artefact left untested. One network family, one seed, gate counts only; no layout or power.

A figure from its own output

Paper, code and results

• README and method
• Experiments and results
• Code
• Tests

More in LLM chip design loops

• Does the MAC-engine lead survive a wider hidden layer (H = 16) and more MAC lanes?Widens the hidden layer to 16 (F = 16, 32) and lets the MAC engine reach P = 16: the best MAC engine still beats the best systolic array, by 1.30x and 1.27x in cells-times-cycles per vector, and at F = 32 its best lane count is again the largest tried (negative, stylised, generic-gate counts).
• Does the MAC-engine lead survive MAC lanes up to P = 32 and arrays up to R = 4?Extends the hidden-16 comparison to MAC lanes up to P = 32 and arrays up to 4x8 with every design simulated: the best MAC engine still wins, by 1.30x and 1.28x in cells-times-cycles per vector; P = 32 adds no cycles over P = 16 (negative, stylised, generic-gate counts).
• Does the MAC engine beat a systolic array under every ABC script, not just Yosys's default?Re-scores chip-systolic-p32's 20 designs under five ABC scripts: the best MAC engine beats the best systolic array in all ten F x script cases, by 1.28x to 1.60x (negative for arrays, stylised, generic-gate counts).
• Is P = 32 being smaller than P = 16 at equal cycles a real effect or a synthesis artefact?Re-synthesises the 16- and 32-lane MAC engines (same cycles) with three seeds and three Yosys flows: the sign of the cell-count gap depends on the flow, with swings of 1-10%, so chip-systolic-p32's 0.7% ranking is not reliable (artefact-sensitive, stylised, generic-gate counts).
• At which Yosys stage does the P = 32 versus P = 16 cell gap appear?Counts cells of the 16- and 32-lane MAC engines after the word-level, bit-level and abc stages: the 32-lane engine is bigger at the word level, about 500 cells smaller after techmap, so the chip-macp32cells gap is set before abc (localised, mechanism unexplained, stylised).
• Which Yosys pass flips the P = 32 versus P = 16 cell gap?Runs the Yosys fine passes one at a time on the 16- and 32-lane MAC engines: the P = 32 versus P = 16 sign flips (+2,100 to about -120 cells) at the first opt -fast after techmap, before any abc, and chip-p32netlist's pre-abc label is corrected (Yosys 0.33's -run :abc includes abc -fast). Stylised.

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.