Does the accumulator-read bug found in accel-gatedmux also inflate accel-planebatch's weight-stationary area?
research/accel-planemux
Does accel-gatedmux's accumulator-read bug also inflate accel-planebatch's WS area? No: the rewritten engine is bit-exact with identical counts and its area is within -3 % to +12 % with no trend (WS/OS 1.62 vs 1.66 at B = 4); the earlier verdict stands.
What it found
accel-gatedmux found that a variable-index accumulator read made the weight-stationary (WS) engines of accel-gatedrtl 17 to 28 % too large. The batched engine of accel-planebatch has the same index. Rewriting its read as an AND-OR over constant indices and its write as decoded enables, and re-running all 40 points (two accel-kws layers, batch 1 to 16, P = 8), gives bit-exact outputs and identical cycles and fetch counts, with WS area between −3 % and +12 % of the original and no trend in batch (WS/OS cells at B = 4: 1.66 before, 1.62 after). Negative: the earlier verdict stands, because here the accumulators are a Verilog array that Yosys already muxes per entry. Generic-gate cells from one mapper run per point, which moves about 3 % by itself.
A figure from its own output

Paper, code and results
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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.