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Why did the gated weight-stationary engine need so much synthesis memory, and does fixing it change its area verdict?

research/accel-gatedmux

Why the gated weight-stationary engine needed so much synthesis memory: one variable-index read of the accumulator bus; an AND-OR read mux gives bit-exact, same-cycle engines 17 to 28 % smaller, gated WS 1.5x OS area at B = 4 and 2.2x at B = 8 (was 1.6 to 1.9x and 2.9 to 3.0x), and lets P = 64 synthesise (stylised).

4 tests

What it found

The accumulator read in the engine of accel-gatedrtl indexed the whole accumulator bus with a variable, which Yosys builds as one wide shifter per lane and which stopped accel-gatedlanes at 16 lanes. An AND-OR read mux over the batch sets gives the same cycles, fetches, accumulator writes and flop count, bit-exact against NumPy at all 48 points (P = 2–64, B = 4 and 8), but weight-stationary engines come out 17–28% smaller in SKY130 HD synthesis (output-stationary unchanged). Gated weight-stationary is 1.45–1.50× the output-stationary area at B = 4 and 2.1–2.2× at B = 8, flat in P, against 1.6–1.9× and 2.9–3.0× before; every point now synthesises under the old 7 GB cap. Stylised: synthesis only, one layer shape, random data, clock-pin-only energy; the cause is inferred from the before-and-after effect.

A figure from its own output

Figure produced by research/accel-gatedmux: gatedmux
accel-gatedmux/experiments/gatedmux.png, written by the project's own experiment code.

Paper, code and results

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.