Does the gated weight-stationary engine's verdict depend on how many lanes it has?

research/accel-gatedlanes

The gated weight-stationary engine's lane count swept from 2 to 16 (32 ran out of synthesis memory): bit-exact, clock-pin energy 1.01 to 1.07x OS with a gate per set at every P, area 1.6 to 1.9x OS at B = 4 and flat from P = 4, so the verdict depends on the batch, not the lanes (stylised).

3 tests

What it found

Sweeps the lane count P (2 to 16, with a failed attempt at 32) of the four engine modes from accel-gatedrtl on the 64×70 keyword-spotting layer, in RTL simulation and Yosys synthesis to SKY130 HD. All 29 points are bit-exact and write the same accumulator bits in every mode. Accumulator clock-pin energy stays at B× OS for ungated WS and at 1.01 to 1.07× with a gate per set, independent of P; gated WS stays 1.6 to 1.9× OS area at B = 4 (2.9 to 3.0× at B = 8), flat from P = 4. So the earlier conclusion (cheap to clock, not small) is a property of the batch, not the lane count. Stylised: synthesis only, clock-pin energy only; Yosys exceeded 7 GB at P = 32, so wider engines are not covered.

A figure from its own output

Figure produced by research/accel-gatedlanes: gatedlanes — accel-gatedlanes/experiments/gatedlanes.png, written by the project's own experiment code.

Paper, code and results

More in Task-specific AI accelerators

Why did the gated weight-stationary engine need so much synthesis memory, and does fixing it change its area verdict?Why the gated weight-stationary engine needed so much synthesis memory: one variable-index read of the accumulator bus; an AND-OR read mux gives bit-exact, same-cycle engines 17 to 28 % smaller, gated WS 1.5x OS area at B = 4 and 2.2x at B = 8 (was 1.6 to 1.9x and 2.9 to 3.0x), and lets P = 64 synthesise (stylised).
Does clock-gated weight-stationary scheduling still beat output-stationary on a second open process, with that process's own SRAM?Second-node verdict for clock-gated register-file weight-stationary scheduling from IHP SG13G2 liberty files (idle flop 34 fJ, clock gate 0.75 of a flop, ten SRAM macros with separate read energies): one gate per accumulator makes WS beat OS in all 120 cells, but ungated WS also wins 33 of 60 packed cells because IHP's SRAM costs 72 to 497 flop-cycles per weight against SKY130's 18 to 62. Library values, not measurements.
Does the accumulator-read bug found in accel-gatedmux also inflate accel-planebatch's weight-stationary area?Does accel-gatedmux's accumulator-read bug also inflate accel-planebatch's WS area? No: the rewritten engine is bit-exact with identical counts and its area is within -3 % to +12 % with no trend (WS/OS 1.62 vs 1.66 at B = 4); the earlier verdict stands.
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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.