Does the clock-gated weight-stationary engine hold up once it is written in RTL and synthesised?
research/accel-gatedrtl
The clock-gated register-file weight-stationary engine in RTL and SKY130 synthesis: bit-exact, same accumulator writes as output-stationary, clock-pin energy 1.0 to 1.07x OS with a gate per set, but area only 7 to 18 % below ungated WS and 1.2 to 5.3x OS (stylised).
What it found
Writes the register-file weight-stationary (WS) engine of accel-planebatch with clock gates (one per 24-bit accumulator, or one per set of eight) and synthesises it to SKY130 HD with Yosys. All 32 points are bit-exact against NumPy and write exactly as many accumulator bits as the output-stationary engine, confirming the assumption of accel-gatedprice. A gate per set brings the accumulator clock-pin energy to 1.00–1.07× output-stationary (ungated WS: B×), but area falls only 7–18 % against ungated WS, and gated WS is still 1.2× to 5.3× the output-stationary area at batch 2 to 16 because the extra accumulator sets are flops either way. Stylised: synthesis only, no place and route, clock tree or timing; energy is a liberty-based clock-pin model.
A figure from its own output
Paper, code and results
More in Task-specific AI accelerators
- Does the gated weight-stationary engine's verdict depend on how many lanes it has?The gated weight-stationary engine's lane count swept from 2 to 16 (32 ran out of synthesis memory): bit-exact, clock-pin energy 1.01 to 1.07x OS with a gate per set at every P, area 1.6 to 1.9x OS at B = 4 and flat from P = 4, so the verdict depends on the batch, not the lanes (stylised).
- Why did the gated weight-stationary engine need so much synthesis memory, and does fixing it change its area verdict?Why the gated weight-stationary engine needed so much synthesis memory: one variable-index read of the accumulator bus; an AND-OR read mux gives bit-exact, same-cycle engines 17 to 28 % smaller, gated WS 1.5x OS area at B = 4 and 2.2x at B = 8 (was 1.6 to 1.9x and 2.9 to 3.0x), and lets P = 64 synthesise (stylised).
- Does clock-gated weight-stationary scheduling still beat output-stationary on a second open process, with that process's own SRAM?Second-node verdict for clock-gated register-file weight-stationary scheduling from IHP SG13G2 liberty files (idle flop 34 fJ, clock gate 0.75 of a flop, ten SRAM macros with separate read energies): one gate per accumulator makes WS beat OS in all 120 cells, but ungated WS also wins 33 of 60 packed cells because IHP's SRAM costs 72 to 497 flop-cycles per weight against SKY130's 18 to 62. Library values, not measurements.
- Does the accumulator-read bug found in accel-gatedmux also inflate accel-planebatch's weight-stationary area?Does
accel-gatedmux's accumulator-read bug also inflateaccel-planebatch's WS area? No: the rewritten engine is bit-exact with identical counts and its area is within -3 % to +12 % with no trend (WS/OS 1.62 vs 1.66 at B = 4); the earlier verdict stands. - How many MAC lanes of a keyword-spotting matrix engine fit on a small open-toolchain FPGA, and which dataflow is fastest there?Accel-plane's output-stationary and reduction-tree engines at 1 to 32 lanes through Yosys and nextpnr-ice40 on an iCE40 UP5K: output-stationary at 16 lanes is fastest that fits (10.2 us per 64x70 product, 2,942 of 5,280 cells); DSP mapping cuts logic 13 to 41% but fails to place beyond 8 lanes. Stylised, synthesis only.
- Does a quantised surrogate make a design search cheaper in finite-element solves than searching with the simulator alone?Does a quantised surrogate make a design search cheaper in FE solves than searching with the simulator alone? At 150 FE evaluations a surrogate-assisted loop is 2.3 to 2.8 % from a best-known design against 6 to 8 % for an FE-only evolution strategy and 14 to 20 % for random search (float and 6-bit surrogates indistinguishable; stylised, 8 seeds).
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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.