Does the weight-stationary advantage in the dataflow model survive RTL at batch above 1, and what does it cost in gates?

What it found

One parameterised Verilog engine implements output- and weight-stationary batched matrix products (P = 8 lanes) for the two accel-kws layer shapes, simulated in Icarus Verilog at batch 1 to 16. All 20 points are bit-exact against NumPy, RTL cycles equal the accel-dataflow schedule model plus a constant 2, and RTL weight and activation fetch counts match the model exactly. Weight-stationary fetches the 4,480 weights of the 64×70 layer once instead of B times at identical cycles, but keeping its partial sums in registers grows the design from 3,024 to 12,284 generic cells (about 192 flops per extra batch element) against a flat ~3,000 for output-stationary. The model's ‘weight-stationary is worst’ ranking came from partial-sum SRAM traffic that this RTL trades for area. Stylised; generic gates, no memories, no energy figures.

A figure from its own output

Paper, code and results

• README and method
• Experiments and results
• Code
• Tests

More in Task-specific AI accelerators

• How cheap must idle flops be, relative to a weight fetch, for register-file weight-stationary to beat output-stationary?Breakeven price ratios from accel-planebatch's RTL counts: register-file weight-stationary beats output-stationary only if an idle flop costs under ~1% of a weight fetch per cycle at batch 4 (falling ~1/B); no energy constant measured (stylised).
• At SKY130's own energy prices, does register-file weight-stationary scheduling beat output-stationary?Places accel-fetchprice's breakevens against SKY130 liberty energies (idle flop 46 fJ per cycle; OpenRAM macro 10 to 90 pJ per access): with weights packed into SRAM words register-file weight-stationary loses to output-stationary at nearly every batch; partial sums in SRAM lose everywhere. Library values, not measurements.
• Does clock-gating the extra accumulators make register-file weight-stationary scheduling beat output-stationary?Prices clock-gated register-file weight-stationary scheduling from SKY130 and GF180 liberty files: an idle clock gate costs 0.86 of an idle flop (SKY130; 0.99 to 1.02 in GF180), so one gate per 24-bit accumulator cuts the idle cost about 28-fold and flips register-file WS from losing to winning against packed SRAM weight fetches in 35 of 64 cells, in all but one cell at 24 flops per gate. Library values, not measurements.
• Does the clock-gated weight-stationary engine hold up once it is written in RTL and synthesised?The clock-gated register-file weight-stationary engine in RTL and SKY130 synthesis: bit-exact, same accumulator writes as output-stationary, clock-pin energy 1.0 to 1.07x OS with a gate per set, but area only 7 to 18 % below ungated WS and 1.2 to 5.3x OS (stylised).
• Does the gated weight-stationary engine's verdict depend on how many lanes it has?The gated weight-stationary engine's lane count swept from 2 to 16 (32 ran out of synthesis memory): bit-exact, clock-pin energy 1.01 to 1.07x OS with a gate per set at every P, area 1.6 to 1.9x OS at B = 4 and flat from P = 4, so the verdict depends on the batch, not the lanes (stylised).
• Why did the gated weight-stationary engine need so much synthesis memory, and does fixing it change its area verdict?Why the gated weight-stationary engine needed so much synthesis memory: one variable-index read of the accumulator bus; an AND-OR read mux gives bit-exact, same-cycle engines 17 to 28 % smaller, gated WS 1.5x OS area at B = 4 and 2.2x at B = 8 (was 1.6 to 1.9x and 2.9 to 3.0x), and lets P = 64 synthesise (stylised).

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.