How large must an activation buffer be before the best dataflow for a small keyword-spotting accelerator changes?
research/accel-dataflowbuf
How large a bounded LRU activation buffer must be before output-stationary stops being the best dataflow for the 40 accel-kws models at batch 4: 32, 64 and 128 words at 8, 16 and 32 lanes (for 10 to 30 of 40 models, input-stationary wins), and not at all at batch 1; buffer-read energy is assumed and no area is charged (stylised).
What it found
A bounded LRU activation buffer of K 8-bit words added to the four accel-dataflow schedules and swept over the 40 accel-kws models at 8, 16 and 32 lanes. At batch 1 output-stationary wins every model at every K. At batch 4 input-stationary first ties or beats it at K = 32, 64 and 128 words (8, 16 and 32 lanes; 10 of 40 models at 8 and 16 lanes, 30 at 32), and no flip occurs for the 2-bit models. If a buffer read costs half an SRAM read instead of a tenth, the flips mostly disappear. Buffer-read energy is assumed and buffer area is not charged. Stylised.
A figure from its own output
Paper, code and results
More in Task-specific AI accelerators
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- At SKY130's own energy prices, does register-file weight-stationary scheduling beat output-stationary?Places accel-fetchprice's breakevens against SKY130 liberty energies (idle flop 46 fJ per cycle; OpenRAM macro 10 to 90 pJ per access): with weights packed into SRAM words register-file weight-stationary loses to output-stationary at nearly every batch; partial sums in SRAM lose everywhere. Library values, not measurements.
- Does clock-gating the extra accumulators make register-file weight-stationary scheduling beat output-stationary?Prices clock-gated register-file weight-stationary scheduling from SKY130 and GF180 liberty files: an idle clock gate costs 0.86 of an idle flop (SKY130; 0.99 to 1.02 in GF180), so one gate per 24-bit accumulator cuts the idle cost about 28-fold and flips register-file WS from losing to winning against packed SRAM weight fetches in 35 of 64 cells, in all but one cell at 24 flops per gate. Library values, not measurements.
- Does the clock-gated weight-stationary engine hold up once it is written in RTL and synthesised?The clock-gated register-file weight-stationary engine in RTL and SKY130 synthesis: bit-exact, same accumulator writes as output-stationary, clock-pin energy 1.0 to 1.07x OS with a gate per set, but area only 7 to 18 % below ungated WS and 1.2 to 5.3x OS (stylised).
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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.