Does NSGA-II find a keyword-spotting accelerator's Pareto front faster than random search at equal budgets?

What it found

NSGA-II against random sampling, 30 seeds each, on a 3,840-design space (40 measured accel-kws models × 6 lane counts × 4 memory-bank counts × 4 supply levels) under a latency deadline, scored against the exact front from exhaustive search. At 20.8% of the space NSGA-II finds 54% and 89% of the exact front's designs (50 and 200 µs deadlines) against 19% and 21% for random search, yet hypervolume is 0.97–1.00 for both, so random search is already good enough if only a near-front is needed. Stylised: bank and supply models are assumptions and no multi-lane RTL was simulated.

A figure from its own output

Paper, code and results

• README and method
• Experiments and results
• Code
• Tests

More in Task-specific AI accelerators

• Was accel-nsga's NSGA-II win a tuning accident? Does population size, mutation rate or crossover change how much of the exact front it finds?Sweeps NSGA-II's population, mutation rate and crossover on the accel-nsga space; mutation 0.02 to 0.1 finds about 0.38 and 0.71 to 0.77 of the exact front at 400 designs, against 0.28 and 0.59 at accel-nsga's setting and 0.13 and 0.12 for random search (stylised).
• Which dataflow should a small keyword-spotting accelerator use, and does the answer survive allowing an input buffer?Weight-, output-, input-stationary and reduction-tree dataflows of a P-lane MAC array on the 40 accel-kws models, from a cycle-by-cycle schedule simulator that matches closed forms exactly and the P = 1 RTL cycles; output-stationary wins on SRAM energy at batch 4 until an input buffer is allowed, then input-mapped flows win at 32 lanes (stylised, assumed energy constants, no RTL for more than one lane).
• How large must an activation buffer be before the best dataflow for a small keyword-spotting accelerator changes?How large a bounded LRU activation buffer must be before output-stationary stops being the best dataflow for the 40 accel-kws models at batch 4: 32, 64 and 128 words at 8, 16 and 32 lanes (for 10 to 30 of 40 models, input-stationary wins), and not at all at batch 1; buffer-read energy is assumed and no area is charged (stylised).
• Does a loop-nest cycle model of a P-lane MAC array match RTL at more than one lane, tails included?P-lane output-stationary and reduction-tree matrix-vector engines in Verilog, bit-exact against NumPy at 1 to 32 lanes, with RTL cycles equal to accel-dataflow's schedule model plus a constant 2 or 3 at every point, tails included (stylised, generic-gate area, batch 1, no memories).
• Does the weight-stationary advantage in the dataflow model survive RTL at batch above 1, and what does it cost in gates?Output- and weight-stationary batched RTL engines at batch 1 to 16: bit-exact, cycles and operand-fetch counts equal accel-dataflow's schedule model, and weight-stationary's saved weight fetches cost up to 4x the generic gates (stylised, P = 8, no memories).
• How cheap must idle flops be, relative to a weight fetch, for register-file weight-stationary to beat output-stationary?Breakeven price ratios from accel-planebatch's RTL counts: register-file weight-stationary beats output-stationary only if an idle flop costs under ~1% of a weight fetch per cycle at batch 4 (falling ~1/B); no energy constant measured (stylised).

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.