What does a product-table inference engine cost in RTL, against a serial MAC engine?
research/accel-lutrtl
The product-table engine and a serial MAC engine in Verilog, bit-exact against NumPy and synthesised with Yosys: negative, the table needs an accumulator per output (stylised)
What it found
Both engines for a 64×N dense layer with 4-bit activations and int8 shared weights, written in Verilog, checked bit for bit against an integer NumPy reference, and synthesised with Yosys to generic gates (assumed gate-equivalent weights). Negative and stylised: the table engine keeps one accumulator per output, so its datapath is 2.4× (N=8) to 11.6× (N=128) the MAC engine's and it takes 1.1× to 3.0× the cycles, even though it stores half the weight bits. Random weights, area only, no energy measured.
A figure from its own output

Paper, code and results
More in Task-specific AI accelerators
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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.