Does block floating point fix the 16-bit FFT scaling problem in an always-on MFCC front end?

What it found

accel-frontend found that fixed per-stage FFT shifts in a 16-bit word either floor quiet speech or overflow loud speech. This project gives the 256-point complex FFT one shared exponent chosen from the data: the block is scaled up to the largest peak a butterfly stage can take (13,573, from the (1 + √2) growth bound) and shifted down by 1 after a stage only when needed. Stored words stay within 16 bits (largest 27,770 over all runs), the butterfly adder needs 17. On the same synthetic voiced frames with a −61 dBFS microphone floor (40 frames per point), cepstral error as a share of cepstral spread is 0.081, 0.060, 0.032 and 0.016 at −60, −50, −40 and −30 dBFS, against 0.715, 0.662, 0.533 and 0.351 for one shift per stage and 0.236, 0.198, 0.120 and 0.051 for a 2-shift schedule that needs 11 to 16-bit adders. At −20 dBFS and above it is about 0.012 to 0.017, no better than fixed schedules that use 18 to 20 bits (0.002 to 0.014): 16-bit rounding sets a floor near 0.01 of the spread. The exponent logic adds 4,608 adds per frame (11,009 to 15,617) and no multiplies, about 0.5% of the front end's modelled energy under accel-frontend's 45 nm constants. Preliminary: those constants were typed from memory of Horowitz (2014) and not re-checked; the audio is synthetic (Speech Commands unreachable), so the metric is cepstral distortion and no keyword accuracy is measured.

A figure from its own output

Paper, code and results

• README and method
• Experiments and results
• Code
• Tests

More in Task-specific AI accelerators

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.