Does ABC's pre-layout delay and area view of 40 MAC engines survive placement and timing repair on SKY130?

research/eda-postplace

The 40 MAC engines placed with the pip OpenROAD wheel: ABC area still ranks placed area (Spearman 0.997+), ABC delay only 0.61 to 0.80, wires add a median 36% to the period, and no design ABC calls feasible at 5 ns meets it after placement.

7 tests

What it found

The eda loops score designs with Yosys and ABC only. Here the 40 MAC-engine designs (1–8 lanes, 4–8 bits) are mapped at two shared targets (5 and 8 ns) and then placed with OpenROAD (the pip install openroad wheel: floorplan, placement, placement-based parasitics, repair_timing; SKY130 HD tt 25 °C). ABC area still ranks repaired area (Spearman 0.997–0.999). ABC delay ranks placed delay at 0.61–0.80, and wires add a median 36% to the period (up to 1.99×; worst for 8-lane arrays). At 5 ns none of the 15 designs ABC calls feasible meets timing after placement; at 8 ns, 39 are feasible in ABC, 1 after placement and 27 after repair for 3.5% median area. Where a front exists it is unchanged (p8, p4, p2, p1 at 4 bits) and p4w4 stays best by area × latency. Limits: no routing or clock tree (the wheel's Tcl floorplan and track commands segfault, so placement parasitics are used), ideal clock, repair stops at timing met so repaired periods are capped, one family, one recipe, one utilisation; not sign-off.

A figure from its own output

Figure produced by research/eda-postplace: placed — eda-postplace/experiments/placed.png, written by the project's own experiment code.

Paper, code and results

More in Algorithmic chip-design loops

Does a cheap rung's rank correlation with the expensive rung predict how well it works as a top-k screen?Across 207 cheap screens of 40 MAC engines, Spearman agreement with SKY130-mapped latency does not predict top-k screening payoff (−0.13 at k = 1): the highest-Spearman screen (0.958) maps the best design first 32% of the time, gate count (0.551) 69%; for area × latency it does (0.60).
If a design search only sees generic-gate numbers, does it find a worse SKY130 Pareto front?Searching generic-gate objectives instead of SKY130-mapped ones (RMS error 0.036 on area, 0.123 on latency) costs within 0.01 of hypervolume on the 40 MAC-engine designs, and TPE's +0.037 lead over random at budget 20 is unchanged.
Can a cost model trained on other chip-design families screen a new family's placed area-period Pareto front, even though period is hard to predict?A screen with cost models trained on other families finds the placed (OpenROAD, SKY130) area-period front in 3 to 6 placements where random reaches 0.92 only at 16, but the true fronts hold only 1 to 2 designs, so the test is easy.
Does generic-gate cell count rank accelerator designs like SKY130-mapped area and clock period?The 40 MAC-engine designs mapped to the SKY130 HD cell library: generic cell count ranks mapped area at Spearman 0.995 but logic depth ranks mapped delay at only 0.611, so the (area, cycles) Pareto front is unchanged while the (area, latency) front loses one design and gains another.
Can an SMT bounded model check (z3) settle the 10 RTL mutants that Yosys' SAT and induction left undecided?Z3 bounded model checking via yosys-smtbmc decides none of the 10 undecided eda-deepdraw survivors at the 24-cycle depth a full inference needs; its cost passes from about 3 s at depth 10 to over 240 s at depth 12.
Does the systolic-array versus MAC-lane verdict survive a shared SKY130 clock target?The 24 systolic-array and MAC-lane designs of chip-systolic mapped to SKY130 at six shared clocks: the MAC-lane engine keeps the best area x latency at every feasible target (arrays 1.61 to 1.66x worse), though the clock removes many arrays and changes the Pareto front.

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.