Does the systolic-array versus MAC-lane verdict survive a shared SKY130 clock target?

research/eda-systolicclock

The 24 systolic-array and MAC-lane designs of chip-systolic mapped to SKY130 at six shared clocks: the MAC-lane engine keeps the best area x latency at every feasible target (arrays 1.61 to 1.66x worse), though the clock removes many arrays and changes the Pareto front.

4 tests

What it found

chip-systolic ranked 4×C systolic arrays against P-lane MAC engines by generic-gate cells × cycles. Here all 24 designs (word length 4, 6, 8; batch of 4) are mapped to SKY130 HD at six shared targets (3–10 ns, map -D T; upsize; dnsize, Yosys 0.33) plus the unconstrained baseline, 168 mappings. A MAC-lane engine (P=4, 4-bit) has the best area × latency at every feasible target; the best array is 1.61× worse unconstrained and 1.66× worse at 5–10 ns. The shared clock removes many arrays (systolic / lane designs meeting the target of 12 each: 0/3 at 4 ns, 2/7 at 5, 8/12 at 10), and the (area, cycles) front changes with T. Limits: ABC combinational delay only, no wires or place and route, one model, one batch size, one recipe.

A figure from its own output

Figure produced by research/eda-systolicclock: tradeoff — eda-systolicclock/experiments/tradeoff.png, written by the project's own experiment code.

Paper, code and results

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What does a good die cost, and at what area do chiplets beat one big die?Cost per good die from five yield models, a dies-per-wafer count and sourced wafer prices and defect densities: a 600 mm² die costs about $179 on a 7nm-class and $359 on a 5nm-class wafer, the yield model moves the 5nm figure by 16%, and two chiplets beat one die from about 300 mm² of logic (range 126-728 mm² over packaging cost and defect density).
How much of an open-source chip design search can cheap fidelity rungs and proof prediction save, with a guarantee?Milestones 1 to 3 done: on 10 designs x 60 ABC pass sequences, the generic-gate score does not rank like routed SKY130 area x delay (tau-b median -0.04), and liberty mapping mis-ranks too when the clock is tight (tau 0.59); at equal wall-clock a one-shot cheap-rung screen does not beat random or hill-climbing search on the cached table; successive halving across rungs does not beat random routed search on mean regret either (plain halving from the generic-gate rung is worst; a 6-point routed pilot to pick the start rung fixes most of that, H3), a 10-point routed pilot plus a conformal bound on the mapped rung keeps the routed optimum 0.99 of the time (nominal 0.90) at 42 to 57% of the routed runs, but on the generic-gate rung coverage fails (0.65 against 0.80, H4 refuted there); proof-success prediction (H5): pooled AUC 0.96 to 0.998 across 15 designs is just design size (an oracle knowing only each design's success rate scores the same), and inside the one design with variation it is 0.65 to 0.78, so H5 is not supported; milestone 6 proves that halving's routed regret is at most the sum of the cut rungs' largest ranking inversions (vacuous for the generic-gate rung, loose for the mapped ones); milestone 7a adds a distribution-free pilot quantile of pair inversions (16-point pilots hold the nominal 0.8 coverage in all 60 group-rung cells, median 0.32 of the maximum), whose summed bound is under 0.1 on 9 of 10 groups for the mapped rungs at a relaxed clock but is violated by realised halving regret in 1 of 40 cells, so it is a heuristic, not a guarantee
Can one harness check, score, cache and log candidate chip designs for any proposer?Unattended design loop (lint, bit-exact RTL sim, gate-netlist check, Yosys synthesis, hash cache, JSONL log, pluggable proposers) run on chip-accel's 40-design grid: synthesis and the gate check are 99% of wall time (stylised, generic-gate counts, no place and route).
Does a space-filling grid order beat the harness's lexicographic order on other chip-design families, or was that luck of one table?Does a space-filling grid order beat the harness's lexicographic one on other families? Lexicographic is arbitrary (worst on MAC, best on FIR); farthest-point beat random from about 6 evaluations on every table, and eda-harness now offers it as an option (stylised, two 36-design families).
Does the order a grid proposer walks a chip-design space change how quickly it finds the Pareto front?Does the order a grid walks a design space matter? The harness's lexicographic grid trails every random order to 30 evaluations; Halton reaches 90% of the front in 7 evaluations against 17 for random (stylised, one table, deterministic orders are single draws).
Which search method finds a chip design's Pareto front with the fewest evaluations?Random, grid, annealing, GA, NSGA-II and TPE at equal budgets by Pareto hypervolume on an 80-design logged space: TPE and NSGA-II lead random from about 16 to 30 evaluations, annealing trails it (stylised, tiny space, untuned).

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What it found

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