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Algorithmic chip-design loops

Does the order a grid proposer walks a chip-design space change how quickly it finds the Pareto front?

research/eda-gridorder

Does the order a grid walks a design space matter? The harness's lexicographic grid trails every random order to 30 evaluations; Halton reaches 90% of the front in 7 evaluations against 17 for random (stylised, one table, deterministic orders are single draws).

7 tests

What it found

The lexicographic grid that the harness ships is replayed against Halton, farthest-point and Latin orders and random shuffles on the 80-design table from eda-proposers (stdlib only, nothing new simulated). Lexicographic scores worse than all 300 random orders up to 30 evaluations and needs 75 evaluations for the whole front; a Halton order reaches 90% of the front's hypervolume in 7 evaluations against a median 17 for random, while random-start farthest-point and Latin orders gain only +0.010 to +0.042 over random from 8 to 20 evaluations and nothing by 40. Stylised: one small table, and the deterministic orders are single draws with no interval.

A figure from its own output

Figure produced by research/eda-gridorder: figure
eda-gridorder/experiments/figure.svg, written by the project's own experiment code.

Paper, code and results

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.