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Algorithmic chip-design loops

Can cheap word-level RTL features predict synthesised cell counts well enough to screen a design search, and does that survive a new design family?

research/eda-surrogate

A cell-count surrogate from cheap word-level RTL features over 133 designs in four generator families: 3.9% median error on families it saw (non-negative linear model), 11% to 210% on a held-out family with rank agreement staying at Spearman 0.75 to 1.00, and it cuts syntheses to find a near-best design in a 36-design pool from 12.4 to 1-5 (stylised, synthesis-only target, no place and route).

12 tests

What it found

A surrogate for Yosys generic-gate cell counts, trained on 24 word-level features (multiplier, adder, mux and register sizes read after proc; opt, about 30× cheaper than synthesis) over 133 designs in four generator families I wrote: MAC engines, FIR filters, ALUs and sorting networks. On families it saw, a non-negative linear cost model has a 3.9% median error and within-family Spearman 0.995, beating boosted trees (8.5%). When a whole family is held out, median errors run from 10.5% to 210.7% and the best model changes with the family, but rank agreement stays at Spearman 0.75–1.00. Ordering a 36-design pool by predicted cells×cycles found a design within 2% of the best after 1–5 syntheses against 12.4 (MAC) and 18.6 (FIR) for random order, both optima sitting at an edge of the space, so the test is weak. Stylised: synthesis-only target, no place and route, small designs.

A figure from its own output

Figure produced by research/eda-surrogate: figure
eda-surrogate/experiments/figure.png, written by the project's own experiment code.

Paper, code and results

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.