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Algorithmic chip-design loops

Which search method finds a chip design's Pareto front with the fewest evaluations?

research/eda-proposers

Random, grid, annealing, GA, NSGA-II and TPE at equal budgets by Pareto hypervolume on an 80-design logged space: TPE and NSGA-II lead random from about 16 to 30 evaluations, annealing trails it (stylised, tiny space, untuned).

10 tests

What it found

Random search, a grid, simulated annealing, a genetic algorithm, NSGA-II and a TPE-style Bayesian method are compared at equal evaluation budgets on an 80-design space (MAC lanes × bit width × ABC script) of a toy quantised-MLP accelerator, using Pareto hypervolume over 100 seeds. TPE reaches 0.917 of the true-front hypervolume at 16 evaluations against 0.891 for random, and 0.980 against 0.943 at 30; annealing trails random throughout. Stylised: the space is tiny (random search at 40 evaluations already scores 0.965), hyperparameters are untuned, objectives are generic-gate counts, and nothing is said about real chips.

A figure from its own output

Figure produced by research/eda-proposers: hv_curves
eda-proposers/experiments/hv_curves.png, written by the project's own experiment code.

Paper, code and results

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.