What does a good die cost, and at what area do chiplets beat one big die?
research/infra-yield
Cost per good die from five yield models, a dies-per-wafer count and sourced wafer prices and defect densities: a 600 mm² die costs about $179 on a 7nm-class and $359 on a 5nm-class wafer, the yield model moves the 5nm figure by 16%, and two chiplets beat one die from about 300 mm² of logic (range 126-728 mm² over packaging cost and defect density).
What it found
Poisson, Murphy, Seeds, Bose-Einstein and negative-binomial yield models, a closed-form dies-per-wafer count checked against an exact grid count, and a chiplet cost model with known-good-die testing and assembly yield. Inputs: CSET's 2020 estimates of TSMC 300 mm wafer prices (9,346 USD at 7 nm, 16,988 USD at 5 nm) and the defect densities TSMC gave in 2020 (0.09 and 0.10–0.11 /cm2, via AnandTech). At negative-binomial α = 3 a 600 mm2 die yields 61 % and costs 179 USD at 7 nm, 55 % and 359 USD at 5 nm; the choice of yield model moves the 5 nm figure from 328 to 382 USD. The closed-form dies-per-wafer count undercounts square dies by 1–12 % (100 to 800 mm2). Two chiplets beat one die from about 300 mm2 of logic at 0.11 /cm2 (assembly 30 USD plus 5 per chiplet), from 126 to 728 mm2 across the swept defect densities and assembly costs; the yield model moves the crossing by 15 %. The cost CSET quotes for a 600 mm2 die is not reproduced (the 5 nm figure is about 238 against 359 here); their die sizes are not known. Assumed, not sourced: the clustering parameter α, the 10 % die-to-die overhead, assembly costs and bond yield (swept). Prices are a 2020 snapshot.
A figure from its own output
Paper, code and results
More in Algorithmic chip-design loops
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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.