Can one harness check, score, cache and log candidate chip designs for any proposer?

What it found

A loop that takes a parameterised generator and a search space and runs each candidate through lint, bit- and cycle-exact RTL simulation, a gate-netlist simulation check and Yosys synthesis, caching by design hash and logging every evaluation as JSON. On chip-accel’s MAC engine (40 designs) all candidates pass; synthesis and the gate-level check take 99% of the 424 s of wall time and RTL simulation under 1%. The Pareto front matches chip-accel’s. A follow-up reuses one Yosys run for the gate check and the score: identical metrics on all 40 designs and 50% less wall time (561 s to 280 s, single timing runs). Stylised: one design family, generic-gate counts, simulation-based (not formal) equivalence, no place and route.

A figure from its own output

Paper, code and results

• README and method
• Experiments and results
• Code
• Tests

More in Algorithmic chip-design loops

• Does a space-filling grid order beat the harness's lexicographic order on other chip-design families, or was that luck of one table?Does a space-filling grid order beat the harness's lexicographic one on other families? Lexicographic is arbitrary (worst on MAC, best on FIR); farthest-point beat random from about 6 evaluations on every table, and eda-harness now offers it as an option (stylised, two 36-design families).
• Does the order a grid proposer walks a chip-design space change how quickly it finds the Pareto front?Does the order a grid walks a design space matter? The harness's lexicographic grid trails every random order to 30 evaluations; Halton reaches 90% of the front in 7 evaluations against 17 for random (stylised, one table, deterministic orders are single draws).
• Which search method finds a chip design's Pareto front with the fewest evaluations?Random, grid, annealing, GA, NSGA-II and TPE at equal budgets by Pareto hypervolume on an 80-design logged space: TPE and NSGA-II lead random from about 16 to 30 evaluations, annealing trails it (stylised, tiny space, untuned).
• Do cheap rungs of the chip-design tool ladder rank designs like synthesis, and how much synthesis time does screening save?A three-rung fidelity ladder (analytic model, RTL simulation, synthesis) over 40 logged designs: the free rung ranks the objective at Spearman 0.74, and successive halving finds the optimum at 20 s of tool time against 205 s to synthesise everything (stylised, toy design family, no place and route).
• Can cheap word-level RTL features predict synthesised cell counts well enough to screen a design search, and does that survive a new design family?A cell-count surrogate from cheap word-level RTL features over 133 designs in four generator families: 3.9% median error on families it saw (non-negative linear model), 11% to 210% on a held-out family with rank agreement staying at Spearman 0.75 to 1.00, and it cuts syntheses to find a near-best design in a 36-design pool from 12.4 to 1-5 (stylised, synthesis-only target, no place and route).
• How many synthesised designs from a new family does a cell-count surrogate need before it is usable, and is it better to pool them with old families or train on them alone?Few-shot adaptation of the eda-surrogate cell-count model to an unseen design family: one synthesised design from the new family cuts the linear model's median error from 49% to 18%, training on the new family alone beats pooling from about three designs, boosted trees need about 12 (stylised, synthesis-only target, no place and route).

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Other research topics

Proper scoring & elicitation28Effort & peer prediction9Verification games & slashing19Detection & tolerances14Markets as routers13Prediction-market design9Paying contributors8Decentralised training systems23Digital twins & sim-to-real164LLM chip design loops40Robot manufacturing loops53Ambient AI assistant46Self-replicating manufacturing34Simulation-first design64Engineered clothing45Task-specific AI accelerators40Algorithmic chip-design loops42Open-source purpose-built robots44The software-engineering loop43Adversarial human imitation41Open-source residential construction41Autonomous multi-angle capture34Sensing, imaging and 3D31Energy supply and dense energy storage39Robot societies among people31Agentic co-design of low-cost robots27Laundry-hanging robots25Machine learning on qualitative data23Robots on the building site27Civilizations & group psychology1History & human sciences1

Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.