If a design search only sees generic-gate numbers, does it find a worse SKY130 Pareto front?

research/eda-rungview

Searching generic-gate objectives instead of SKY130-mapped ones (RMS error 0.036 on area, 0.123 on latency) costs within 0.01 of hypervolume on the 40 MAC-engine designs, and TPE's +0.037 lead over random at budget 20 is unchanged.

6 tests

What it found

eda-noisy injected synthetic Gaussian error into the objectives a proposer sees. Here the error is measured: on the 40 MAC-engine designs, proposers search generic-gate objectives (cells, cycles, optionally cycles × depth) and are scored on SKY130-mapped area and latency from eda-sky130rung (Yosys 0.33, ABC dc2; map, pinned ORFS commit). The generic views differ from the mapped truth by RMS 0.036 (area) and 0.123 (latency) of each objective’s range, yet searching them costs within ±0.01 of hypervolume against searching the truth, and TPE’s lead over random at budget 20 is unchanged (+0.037, 95% CI +0.032 to +0.042, 200 paired seeds). iid noise at the matched level gives a similar answer; at σ = 0.2 it does cost TPE 0.012. Limits: one toy design family, one ABC script, no place and route (not sign-off), and the error objective is shared by both views.

A figure from its own output

Figure produced by research/eda-rungview: gain_by_view — eda-rungview/experiments/gain_by_view.png, written by the project's own experiment code.

Paper, code and results

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Can a cost model trained on other chip-design families screen a new family's placed area-period Pareto front, even though period is hard to predict?A screen with cost models trained on other families finds the placed (OpenROAD, SKY130) area-period front in 3 to 6 placements where random reaches 0.92 only at 16, but the true fronts hold only 1 to 2 designs, so the test is easy.
Does generic-gate cell count rank accelerator designs like SKY130-mapped area and clock period?The 40 MAC-engine designs mapped to the SKY130 HD cell library: generic cell count ranks mapped area at Spearman 0.995 but logic depth ranks mapped delay at only 0.611, so the (area, cycles) Pareto front is unchanged while the (area, latency) front loses one design and gains another.
Can an SMT bounded model check (z3) settle the 10 RTL mutants that Yosys' SAT and induction left undecided?Z3 bounded model checking via yosys-smtbmc decides none of the 10 undecided eda-deepdraw survivors at the 24-cycle depth a full inference needs; its cost passes from about 3 s at depth 10 to over 240 s at depth 12.
Does the systolic-array versus MAC-lane verdict survive a shared SKY130 clock target?The 24 systolic-array and MAC-lane designs of chip-systolic mapped to SKY130 at six shared clocks: the MAC-lane engine keeps the best area x latency at every feasible target (arrays 1.61 to 1.66x worse), though the clock removes many arrays and changes the Pareto front.
What does a good die cost, and at what area do chiplets beat one big die?Cost per good die from five yield models, a dies-per-wafer count and sourced wafer prices and defect densities: a 600 mm² die costs about $179 on a 7nm-class and $359 on a 5nm-class wafer, the yield model moves the 5nm figure by 16%, and two chiplets beat one die from about 300 mm² of logic (range 126-728 mm² over packaging cost and defect density).
How much of an open-source chip design search can cheap fidelity rungs and proof prediction save, with a guarantee?Milestones 1 to 3 done: on 10 designs x 60 ABC pass sequences, the generic-gate score does not rank like routed SKY130 area x delay (tau-b median -0.04), and liberty mapping mis-ranks too when the clock is tight (tau 0.59); at equal wall-clock a one-shot cheap-rung screen does not beat random or hill-climbing search on the cached table; successive halving across rungs does not beat random routed search on mean regret either (plain halving from the generic-gate rung is worst; a 6-point routed pilot to pick the start rung fixes most of that, H3), a 10-point routed pilot plus a conformal bound on the mapped rung keeps the routed optimum 0.99 of the time (nominal 0.90) at 42 to 57% of the routed runs, but on the generic-gate rung coverage fails (0.65 against 0.80, H4 refuted there); proof-success prediction (H5): pooled AUC 0.96 to 0.998 across 15 designs is just design size (an oracle knowing only each design's success rate scores the same), and inside the one design with variation it is 0.65 to 0.78, so H5 is not supported; milestone 6 proves that halving's routed regret is at most the sum of the cut rungs' largest ranking inversions (vacuous for the generic-gate rung, loose for the mapped ones); milestone 7a adds a distribution-free pilot quantile of pair inversions (16-point pilots hold the nominal 0.8 coverage in all 60 group-rung cells, median 0.32 of the maximum), whose summed bound is under 0.1 on 9 of 10 groups for the mapped rungs at a relaxed clock but is violated by realised halving regret in 1 of 40 cells, so it is a heuristic, not a guarantee

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What it found

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