Does generic-gate cell count rank accelerator designs like SKY130-mapped area and clock period?

research/eda-sky130rung

The 40 MAC-engine designs mapped to the SKY130 HD cell library: generic cell count ranks mapped area at Spearman 0.995 but logic depth ranks mapped delay at only 0.611, so the (area, cycles) Pareto front is unchanged while the (area, latency) front loses one design and gains another.

6 tests

What it found

The 40 MAC-engine designs of eda-harness (1–8 lanes, 4–8 bits) were mapped to the SKY130 HD standard-cell library (Yosys 0.33, ABC dc2; map, flip-flops mapped with dfflibmap, tt 25 °C 1.80 V liberty at a pinned ORFS commit). Generic-gate cell count ranks mapped area almost perfectly (Spearman 0.995, Kendall 0.954; 6.4–8.4 µm² per generic cell), but logic depth ranks ABC's mapped critical-path delay only at Spearman 0.611. So the (cells, cycles) Pareto front is identical to the (area, cycles) front, yet adding clock period moves it: with latency = cycles × delay, one of four generic-front designs drops off and a 5-bit design joins; top-5 overlap on the combined objective is 0.60. Limits: one design family, one ABC script, unconstrained map delay with no wires or placement, no place and route (not installed), so none of it is sign-off or silicon.

A figure from its own output

Figure produced by research/eda-sky130rung: rungs — eda-sky130rung/experiments/rungs.png, written by the project's own experiment code.

Paper, code and results

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Can an SMT bounded model check (z3) settle the 10 RTL mutants that Yosys' SAT and induction left undecided?Z3 bounded model checking via yosys-smtbmc decides none of the 10 undecided eda-deepdraw survivors at the 24-cycle depth a full inference needs; its cost passes from about 3 s at depth 10 to over 240 s at depth 12.
Does the systolic-array versus MAC-lane verdict survive a shared SKY130 clock target?The 24 systolic-array and MAC-lane designs of chip-systolic mapped to SKY130 at six shared clocks: the MAC-lane engine keeps the best area x latency at every feasible target (arrays 1.61 to 1.66x worse), though the clock removes many arrays and changes the Pareto front.
What does a good die cost, and at what area do chiplets beat one big die?Cost per good die from five yield models, a dies-per-wafer count and sourced wafer prices and defect densities: a 600 mm² die costs about $179 on a 7nm-class and $359 on a 5nm-class wafer, the yield model moves the 5nm figure by 16%, and two chiplets beat one die from about 300 mm² of logic (range 126-728 mm² over packaging cost and defect density).
How much of an open-source chip design search can cheap fidelity rungs and proof prediction save, with a guarantee?Milestones 1 to 3 done: on 10 designs x 60 ABC pass sequences, the generic-gate score does not rank like routed SKY130 area x delay (tau-b median -0.04), and liberty mapping mis-ranks too when the clock is tight (tau 0.59); at equal wall-clock a one-shot cheap-rung screen does not beat random or hill-climbing search on the cached table; successive halving across rungs does not beat random routed search on mean regret either (plain halving from the generic-gate rung is worst; a 6-point routed pilot to pick the start rung fixes most of that, H3), a 10-point routed pilot plus a conformal bound on the mapped rung keeps the routed optimum 0.99 of the time (nominal 0.90) at 42 to 57% of the routed runs, but on the generic-gate rung coverage fails (0.65 against 0.80, H4 refuted there); proof-success prediction (H5): pooled AUC 0.96 to 0.998 across 15 designs is just design size (an oracle knowing only each design's success rate scores the same), and inside the one design with variation it is 0.65 to 0.78, so H5 is not supported; milestone 6 proves that halving's routed regret is at most the sum of the cut rungs' largest ranking inversions (vacuous for the generic-gate rung, loose for the mapped ones); milestone 7a adds a distribution-free pilot quantile of pair inversions (16-point pilots hold the nominal 0.8 coverage in all 60 group-rung cells, median 0.32 of the maximum), whose summed bound is under 0.1 on 9 of 10 groups for the mapped rungs at a relaxed clock but is violated by realised halving regret in 1 of 40 cells, so it is a heuristic, not a guarantee
Can one harness check, score, cache and log candidate chip designs for any proposer?Unattended design loop (lint, bit-exact RTL sim, gate-netlist check, Yosys synthesis, hash cache, JSONL log, pluggable proposers) run on chip-accel's 40-design grid: synthesis and the gate check are 99% of wall time (stylised, generic-gate counts, no place and route).
Does a space-filling grid order beat the harness's lexicographic order on other chip-design families, or was that luck of one table?Does a space-filling grid order beat the harness's lexicographic one on other families? Lexicographic is arbitrary (worst on MAC, best on FIR); farthest-point beat random from about 6 evaluations on every table, and eda-harness now offers it as an option (stylised, two 36-design families).

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What it found

A figure from its own output

Paper, code and results

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