Does a cheap rung's rank correlation with the expensive rung predict how well it works as a top-k screen?

What it found

The eda projects judge cheap proxies by Spearman rank correlation with the SKY130-mapped objective, but a search loop only uses the top of the proxy's list. Over 207 screens of the 40 MAC-engine designs of eda-sky130rung (7 named proxies from eda-delayproxy and 200 random re-weightings of its logical-effort delay; Yosys 0.33, ABC dc2; map, SKY130 HD), agreement predicts payoff only when the screens already rank well. For mapped area × latency, across screens Spearman agreement and the chance that the pool's best design is among the first mapped correlate at 0.60 (bootstrap 0.50 to 0.68). For mapped latency alone they do not (−0.13, −0.26 to 0.02): the highest-Spearman screen (0.958) maps the best design first only 0.324 of the time, while gate count, at Spearman 0.551, does so 0.692, and 14 of 175 screens with Spearman ≥ 0.9 do not put the true best in their top 3. The best design's rank in the screen's order predicts payoff (0.90 for latency) but a loop cannot compute it without the mapping. The area × latency screens reproduce eda-latencyhalve's 0.636 and 0.970. Preliminary: one design family, one ABC script, no place and route; the swept screens are correlated variants of one model, so the bootstrap over screens is optimistic.

A figure from its own output

Paper, code and results

• README and method
• Experiments and results
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More in Algorithmic chip-design loops

• If a design search only sees generic-gate numbers, does it find a worse SKY130 Pareto front?Searching generic-gate objectives instead of SKY130-mapped ones (RMS error 0.036 on area, 0.123 on latency) costs within 0.01 of hypervolume on the 40 MAC-engine designs, and TPE's +0.037 lead over random at budget 20 is unchanged.
• Can a cost model trained on other chip-design families screen a new family's placed area-period Pareto front, even though period is hard to predict?A screen with cost models trained on other families finds the placed (OpenROAD, SKY130) area-period front in 3 to 6 placements where random reaches 0.92 only at 16, but the true fronts hold only 1 to 2 designs, so the test is easy.
• Does generic-gate cell count rank accelerator designs like SKY130-mapped area and clock period?The 40 MAC-engine designs mapped to the SKY130 HD cell library: generic cell count ranks mapped area at Spearman 0.995 but logic depth ranks mapped delay at only 0.611, so the (area, cycles) Pareto front is unchanged while the (area, latency) front loses one design and gains another.
• Can an SMT bounded model check (z3) settle the 10 RTL mutants that Yosys' SAT and induction left undecided?Z3 bounded model checking via yosys-smtbmc decides none of the 10 undecided eda-deepdraw survivors at the 24-cycle depth a full inference needs; its cost passes from about 3 s at depth 10 to over 240 s at depth 12.
• Does the systolic-array versus MAC-lane verdict survive a shared SKY130 clock target?The 24 systolic-array and MAC-lane designs of chip-systolic mapped to SKY130 at six shared clocks: the MAC-lane engine keeps the best area x latency at every feasible target (arrays 1.61 to 1.66x worse), though the clock removes many arrays and changes the Pareto front.
• What does a good die cost, and at what area do chiplets beat one big die?Cost per good die from five yield models, a dies-per-wafer count and sourced wafer prices and defect densities: a 600 mm² die costs about $179 on a 7nm-class and $359 on a 5nm-class wafer, the yield model moves the 5nm figure by 16%, and two chiplets beat one die from about 300 mm² of logic (range 126-728 mm² over packaging cost and defect density).

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.