Can RTL checks that need no golden reference model catch the bugs a design loop injects?
research/eda-goldenfree
Five golden-free properties (latency, done pulse, output hold, start-glitch and reset-abort invariance) kill 22 of the 66 killable eda-verify mutants, all control-flow bugs, and none of the 15 ROM or other datapath bugs; the 16 directed vectors catch all 22 too.
What it found
A design loop that generates unseen RTL has no trusted reference output, so this project scores five properties that need only the spec's 20-cycle latency and the module's own repeatability on the 91 compilable eda-verify mutants of the MAC engine. They kill 22 of the 66 killable mutants (0.33) and flag none of the 16 proved-equivalent or 9 undecided ones. Every kill is a latency change or hang; all datapath mutants (including all 15 ROM edits) pass, since a wrong value is still timed and repeatable. The 16 coverage-directed vectors with a golden model catch all 22 as well and 40 more, so the golden-free checks add nothing on this design. Preliminary: one design, five author-chosen properties, simulation only; value-level properties and a formal check were not tried.
Paper, code and results
More in Algorithmic chip-design loops
- How many SKY130 mappings does a generic-gate screen need to find the best area × latency design?A generic-gate cells × cycles screen puts the best SKY130 area × latency design first among 40 MAC engines; over random pools of 20, mapping 3 designs finds the pool's best 97% of the time, against 15% for random choice.
- Does ABC's pre-layout delay and area view of 40 MAC engines survive placement and timing repair on SKY130?The 40 MAC engines placed with the pip OpenROAD wheel: ABC area still ranks placed area (Spearman 0.997+), ABC delay only 0.61 to 0.80, wires add a median 36% to the period, and no design ABC calls feasible at 5 ns meets it after placement.
- Does a cheap rung's rank correlation with the expensive rung predict how well it works as a top-k screen?Across 207 cheap screens of 40 MAC engines, Spearman agreement with SKY130-mapped latency does not predict top-k screening payoff (−0.13 at k = 1): the highest-Spearman screen (0.958) maps the best design first 32% of the time, gate count (0.551) 69%; for area × latency it does (0.60).
- If a design search only sees generic-gate numbers, does it find a worse SKY130 Pareto front?Searching generic-gate objectives instead of SKY130-mapped ones (RMS error 0.036 on area, 0.123 on latency) costs within 0.01 of hypervolume on the 40 MAC-engine designs, and TPE's +0.037 lead over random at budget 20 is unchanged.
- Can a cost model trained on other chip-design families screen a new family's placed area-period Pareto front, even though period is hard to predict?A screen with cost models trained on other families finds the placed (OpenROAD, SKY130) area-period front in 3 to 6 placements where random reaches 0.92 only at 16, but the true fronts hold only 1 to 2 designs, so the test is easy.
- Does generic-gate cell count rank accelerator designs like SKY130-mapped area and clock period?The 40 MAC-engine designs mapped to the SKY130 HD cell library: generic cell count ranks mapped area at Spearman 0.995 but logic depth ranks mapped delay at only 0.611, so the (area, cycles) Pareto front is unchanged while the (area, latency) front loses one design and gains another.
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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.