Do the SKY130 area and latency conclusions for a MAC-engine family survive a target clock period?
research/eda-clocksweep
The 40 MAC-engine designs mapped to SKY130 at six shared clock targets: cell count still ranks area (Spearman 0.995+), logic depth ranks delay at only 0.34 to 0.82, and with one shared clock the Pareto front equals the generic one, so the earlier front change came from per-design clocks.
What it found
eda-sky130rung mapped each of 40 MAC-engine designs with an unconstrained ABC map, so each ran at its own clock. Here every design is mapped at six shared targets (3–10 ns, map -D T; upsize; dnsize, Yosys 0.33, SKY130 HD tt 25 °C) plus the baseline, 280 mappings. Cell count still ranks area (Spearman 0.995–0.996 at every setting). Logic depth ranks delay at only 0.34–0.82 depending on T, never reliably. No design reaches 3 ns; 6, 15, 25, 39 and 40 of 40 meet 4, 5, 6, 8 and 10 ns. With one shared clock the feasible (area, cycles) front equals the generic front (p8, p4, p2, p1 at 4 bits; p8 drops out at 4 ns), and p4w4 is the best area × latency design at every feasible T, so the front change reported with per-design clocks came from the clocks, not the cell library. Limits: ABC combinational delay only (no wires, clock tree or placement), one family, one recipe, no place and route, so none of it is sign-off or silicon.
A figure from its own output
Paper, code and results
More in Algorithmic chip-design loops
- Do 20,000 random vectors catch any RTL bug that 64 missed, and do they contradict the formal equivalence proofs?20,000 further random vectors catch none of the 25 eda-verify survivors, so none contradicts a formal equivalence proof; a random-visible bug among the 9 formal timeouts has per-vector detection probability below 1.4e-4.
- Can a library-free delay estimate rank accelerator designs by SKY130 critical-path delay better than logic depth?Library-free delay proxies on the generic gate netlist of the 40 MAC engines: gate-type weights leave depth's Spearman 0.611 against SKY130-mapped delay unchanged (0.609), adding fan-out lifts it to 0.83 to 0.90, but gate count alone reaches 0.911, and no proxy recovers the true (area, latency) front.
- How many random vectors does it take to see an RTL bug, and what can 1,280 clean vectors not rule out?Per-vector detection probabilities of the eda-verify mutants: a geometric model fits the random-vector miss rate within 0.005, predicts 45 vectors for a 1% miss, and 1,280 clean vectors cannot rule out a bug rarer than 0.0023 per vector (stylised re-analysis).
- Can RTL checks that need no golden reference model catch the bugs a design loop injects?Five golden-free properties (latency, done pulse, output hold, start-glitch and reset-abort invariance) kill 22 of the 66 killable eda-verify mutants, all control-flow bugs, and none of the 15 ROM or other datapath bugs; the 16 directed vectors catch all 22 too.
- How many SKY130 mappings does a generic-gate screen need to find the best area × latency design?A generic-gate cells × cycles screen puts the best SKY130 area × latency design first among 40 MAC engines; over random pools of 20, mapping 3 designs finds the pool's best 97% of the time, against 15% for random choice.
- Does ABC's pre-layout delay and area view of 40 MAC engines survive placement and timing repair on SKY130?The 40 MAC engines placed with the pip OpenROAD wheel: ABC area still ranks placed area (Spearman 0.997+), ABC delay only 0.61 to 0.80, wires add a median 36% to the period, and no design ABC calls feasible at 5 ns meets it after placement.
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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.