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Algorithmic chip-design loops

Can a library-free delay estimate rank accelerator designs by SKY130 critical-path delay better than logic depth?

research/eda-delayproxy

Library-free delay proxies on the generic gate netlist of the 40 MAC engines: gate-type weights leave depth's Spearman 0.611 against SKY130-mapped delay unchanged (0.609), adding fan-out lifts it to 0.83 to 0.90, but gate count alone reaches 0.911, and no proxy recovers the true (area, latency) front.

5 tests

What it found

eda-sky130rung found that generic logic depth ranks SKY130-mapped critical-path delay at only Spearman 0.611 over 40 MAC-engine designs. This project computes cheap delay proxies on the same generic gate netlist (Yosys 0.33 write_json) and ranks them against the mapped delay: weighting gates by type (logical-effort constants from Sutherland, Sproull and Harris 1999) changes nothing (0.609), while adding fan-out lifts agreement to 0.83 (logical effort with real fan-out) and 0.90 (a type-blind fan-out model). Gate count alone reaches 0.911, so on this family delay is largely size. All 200 random re-weightings of gate types beat unit depth (0.667 to 0.911). Replacing the mapped delay by any proxy in area × cycles × delay finds the same best design but misses the 5-bit design the true (area, latency) front gains (3 of 4 front members for every proxy). Limits: one design family, one ABC script, mapped delay from ABC stime without wires or place and route; the 0.5 fan-out coefficient is not sourced; not sign-off.

A figure from its own output

Figure produced by research/eda-delayproxy: proxies
eda-delayproxy/experiments/proxies.png, written by the project's own experiment code.

Paper, code and results

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.