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Algorithmic chip-design loops

When can a check cascade stop formal verification early without losing kills?

research/eda-earlystop

Replays the eda-verify log with a time cap on formal: a 170 s cap loses no kill and saves 41% of cascade CPU but forfeits every equivalence proof; a 230 s cap keeps 15 of 16 proofs and saves 23% (stylised re-analysis).

7 tests

What it found

Replay of the eda-verify mutation log with a time cap on the formal stage. Every formal kill in the log finished within 164 s, while equivalence proofs take about 222 s, so a 170 s cap loses no kill (66 of 66 killable mutants still found) and saves 41% of the cascade's CPU, but gives up all 16 equivalence proofs; a 230 s cap keeps 15 of them and saves 23%. Caps of 30 s or less start losing kills. A cap learned from half the mutants worked on the other half when the training half contained formal kills and failed (1.6 of 29 kills lost) when it contained none. Stylised: one design, one solver, 91 mutants; nothing new was simulated.

A figure from its own output

Figure produced by research/eda-earlystop: figure
eda-earlystop/experiments/figure.svg, written by the project's own experiment code.

Paper, code and results

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.