How much of a surrogate screen’s lead over random search comes from the free objectives?

What it found

A follow-up to eda-screen on the same 80-design accelerator table. A random search that uses the free cycles and error objectives (no cell-count model) finds 0.901 of the true front’s hypervolume at 12 syntheses, against 0.860 for plain random, 0.878 for TPE and 0.990 for the 4-fit screen (100 seeds). So +0.041 of the screen’s +0.130 lead comes from the free objectives and +0.089 from the surrogate. The baseline stalls once the free-objective layer is spent and falls below random and TPE by 30 syntheses. Stylised: one 80-design space, generic-gate cell counts, no place and route.

A figure from its own output

Paper, code and results

• README and method
• Experiments and results
• Code
• Tests

More in Algorithmic chip-design loops

• Can a cost model trained on other chip-design families screen a new family’s Pareto front with a handful of syntheses?A Pareto screen whose cell-count model was trained only on other design families reaches 0.94 to 0.98 of the true front's hypervolume with 3 Yosys syntheses (random about 0.65), though the model's absolute error is large; ranking is what matters (stylised, MAC and FIR spaces of 27 designs).
• Does the best ABC recipe for one design transfer to another?All 400 ABC pass sequences on eight small SKY130-mapped designs: one design's best recipe scores a mean 1.31× the other's optimum, and a transferred warm start helps only one design (stylised, toy designs, no place and route).
• How many injected RTL bugs do random, coverage-directed and formal checks catch, and at what cost?Mutation study of random, coverage-directed and bounded-formal RTL checks on the MAC accelerator: 64 random vectors kill 99% of killable mutants, formal 71% (timeouts), at ~50x the CPU cost (stylised).
• In what order should an automated design loop run random, directed and formal checks?Replays the eda-verify mutation log to cost check cascades: random simulation before formal cuts CPU by 54% with more kills; the order among cheap stages barely matters (stylised re-analysis).
• When can a check cascade stop formal verification early without losing kills?Replays the eda-verify log with a time cap on formal: a 170 s cap loses no kill and saves 41% of cascade CPU but forfeits every equivalence proof; a 230 s cap keeps 15 of 16 proofs and saves 23% (stylised re-analysis).
• Can cheap features say which simulation survivors formal can prove equivalent?Predicts from the mutated source line which simulation survivors formal can prove equivalent: nearest-line prediction cuts formal CPU 55% and finds 14 of 16 proofs on one design (stylised, 27 mutants).

All 42 Algorithmic chip-design loops projects →

Other research topics

Proper scoring & elicitation28Effort & peer prediction9Verification games & slashing19Detection & tolerances14Markets as routers13Prediction-market design9Paying contributors8Decentralised training systems23Digital twins & sim-to-real164LLM chip design loops40Robot manufacturing loops53Ambient AI assistant46Self-replicating manufacturing34Simulation-first design64Engineered clothing45Task-specific AI accelerators40Algorithmic chip-design loops42Open-source purpose-built robots44The software-engineering loop43Adversarial human imitation41Open-source residential construction41Autonomous multi-angle capture34Sensing, imaging and 3D31Energy supply and dense energy storage39Robot societies among people31Agentic co-design of low-cost robots27Laundry-hanging robots25Machine learning on qualitative data23Robots on the building site27Civilizations & group psychology1History & human sciences1

Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.